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2012 13th Latin American Test Workshop (LATW)最新文献

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Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical path 基于每个逻辑路径的传播延迟，应用自适应时序滤波进行SET缓解
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261257
Jose Eduardo Pereira Souza, F. Kastensmidt
{"title":"Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical path","authors":"Jose Eduardo Pereira Souza, F. Kastensmidt","doi":"10.1109/LATW.2012.6261257","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261257","url":null,"abstract":"This paper proposes the use of a programmable radiation hardened flip-flop to select the most appropriate delay in the SET temporal filtering for each flip-flop in a circuit. Each flip-flop can filter SETs by using different delays based on the propagation-delay of its logical path. The propagation-delay variances among multiple paths can be used to increase or reduce the delay of the SET filtering. In this way, a delay with a minimum performance impact can always be selected. This approach was validated by electrical simulations in a case-study circuit Different SET pulse widths were injected. Results have shown the efficiently of this technique to filter SETs and to tolerate SEUs in integrated circuits.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116078579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pattern-based injections in processors implemented on SRAM-based FPGAs 在基于sram的fpga上实现的基于模式的处理器注入
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261263
M. Jrad, R. Leveugle
{"title":"Pattern-based injections in processors implemented on SRAM-based FPGAs","authors":"M. Jrad, R. Leveugle","doi":"10.1109/LATW.2012.6261263","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261263","url":null,"abstract":"Multiple errors are an increasing concern for designers. Multiple errors in the configuration memory have to be taken into account when a circuit is implemented on a SRAM-based FPGA. This paper reports on the impact of realistic multiple-bit errors in the configuration, with respect to the robustness of a processor with error detection mechanisms.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115868831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test 内置自诊断针对任意缺陷与部分伪穷举测试
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261229
A. Cook, S. Hellebrand, M. Imhof, A. Mumtaz, H. Wunderlich
{"title":"Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test","authors":"A. Cook, S. Hellebrand, M. Imhof, A. Mumtaz, H. Wunderlich","doi":"10.1109/LATW.2012.6261229","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261229","url":null,"abstract":"Pseudo-exhaustive test completely verifies all output functions of a combinational circuit, which provides a high coverage of non-target faults and allows an efficient on-chip implementation. To avoid long test times caused by large output cones, partial pseudo-exhaustive test (P-PET) has been proposed recently. Here only cones with a limited number of inputs are tested exhaustively, and the remaining faults are targeted with deterministic patterns. Using P-PET patterns for built-in diagnosis, however, is challenging because of the large amount of associated response data. This paper presents a built-in diagnosis scheme which only relies on sparsely distributed data in the response sequence, but still preserves the benefits of P-PET.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133935365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-power design under variation using error prevention and error tolerance (invited paper) 基于防错和容错的低功耗设计(特邀论文)
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261232
Kwanyeob Chae, M. Cho, S. Mukhopadhyay
{"title":"Low-power design under variation using error prevention and error tolerance (invited paper)","authors":"Kwanyeob Chae, M. Cho, S. Mukhopadhyay","doi":"10.1109/LATW.2012.6261232","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261232","url":null,"abstract":"This paper presents error tolerance and error prevention methodologies to reduce power dissipation in digital circuits under process variations. For logic circuits, timing error prevention using time-borrowing and clock stretching is discussed as a feasible approach to reduce power dissipation for a target throughput. The natural error tolerance in image processing applications is exploited to reduce power dissipations in Static Random Access Memory (SRAM).","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132280891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PSL assertion checkers synthesis with ASM based HLS tool ABELITE 使用基于ASM的HLS工具ABELITE合成PSL断言检查器
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261251
M. Jenihhin, S. Baranov, J. Raik, Valentin Tihhomirov
{"title":"PSL assertion checkers synthesis with ASM based HLS tool ABELITE","authors":"M. Jenihhin, S. Baranov, J. Raik, Valentin Tihhomirov","doi":"10.1109/LATW.2012.6261251","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261251","url":null,"abstract":"This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134633938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Variation-aware and self-healing design methodology for a system-on-chip 片上系统的变化感知和自修复设计方法
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261233
Jangjoon Lee, Srikar Bhagavatula, K. Roy, B. Jung
{"title":"Variation-aware and self-healing design methodology for a system-on-chip","authors":"Jangjoon Lee, Srikar Bhagavatula, K. Roy, B. Jung","doi":"10.1109/LATW.2012.6261233","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261233","url":null,"abstract":"Due to high sensitivity to process, supply, and temperature variations, deep scaled technologies are losing appeal. Analog and mixed-signal circuits have failed to exploit high speed and low noise properties of these technologies due to marginalities, whereas variations in leakage current and delay have made digital design extremely challenging. Consequently, there is an increasing need for a new design methodology that can provide high yield and improved reliability under PVT variations. Among several post-fabrication calibration strategies, self-healing, which is based on real-time sensing and built-in feedback, has generated great interest because of the ability to dynamically adapt to parametric variations. This paper examines current built-in variation-aware and ad-hoc self-healing designs, and discusses the challenges and strategies in developing a coherent self-healing methodology for system-on-chip (SoC) design in deep-scaled CMOS technologies.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114642958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis 利用关键路径追踪和突变分析对多重设计错误进行诊断和修正
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261234
Hanno Hantson, Urmas Repinski, J. Raik, M. Jenihhin, R. Ubar
{"title":"Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis","authors":"Hanno Hantson, Urmas Repinski, J. Raik, M. Jenihhin, R. Ubar","doi":"10.1109/LATW.2012.6261234","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261234","url":null,"abstract":"Identification of the presence of design errors, i.e. verification is a well-studied field with a range of methods developed. Yet, most of the verification cycle is consumed for debugging, which consists of localization and correction of errors. Current paper presents a method for automated debug of multiple simultaneous design errors for RTL designs. We propose a critical path tracing based error localization method, which performs statistical analysis in order to rank suspected error locations. Then, an error matching approach to correction is applied implementing mutation operations. Experiments carried out in this work analyze localizing multiple erroneous data operations and their mutation-based correction. We compare two metrics of statistical analysis and show their capabilities in localizing multiple errors.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SITARe: A simulation tool for analysis and diagnosis of radiation effects SITARe:用于分析和诊断辐射效应的模拟工具
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261254
G. Micolau, K. Castellani-Coulié, H. Aziza, J. Portal
{"title":"SITARe: A simulation tool for analysis and diagnosis of radiation effects","authors":"G. Micolau, K. Castellani-Coulié, H. Aziza, J. Portal","doi":"10.1109/LATW.2012.6261254","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261254","url":null,"abstract":"This work provides reliability criteria to detect and diagnose multi-events upset by the use of a SER tool. The study is based on a charge generation model used to simulate the impact of an ionizing particle striking the sensitive nodes of a SRAM cell. The currents, collected at the sensitive nodes are generated by the physical model and injected at circuit level. Thus, a correlation between the circuit electrical behavior and injected currents is established to provide a reliability criterion.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Automatic generation of an FPGA based embedded test system for printed circuit board testing 基于FPGA的嵌入式印刷电路板测试系统的自动生成
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261241
Jorge Hernán Meza Escobar, J. SachBe, Steffen Ostendorff, H. Wuttke
{"title":"Automatic generation of an FPGA based embedded test system for printed circuit board testing","authors":"Jorge Hernán Meza Escobar, J. SachBe, Steffen Ostendorff, H. Wuttke","doi":"10.1109/LATW.2012.6261241","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261241","url":null,"abstract":"This paper describes an FPGA based embedded test system, designed for testing of printed circuit boards during the manufacturing process. The test system architecture is automatically generated based on a layer description, which provides the required flexibility for the generation of the test system, and for the abstraction of the test functions. The test system is composed of a software and a hardware part, and generated based on the board's properties and the specified test algorithms. The paper presents the test system architecture and automatic generation flow, with emphasis on the software generation process. The paper also includes experimental results obtained when performing an SRAM interconnection test.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Investigation of a CMOS oscillator concept for particle detection and diagnosis 一种用于粒子检测与诊断的CMOS振荡器概念研究
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261253
K. Castellani-Coulié, H. Aziza, W. Rahajandraibe, G. Micolau, J. Portal
{"title":"Investigation of a CMOS oscillator concept for particle detection and diagnosis","authors":"K. Castellani-Coulié, H. Aziza, W. Rahajandraibe, G. Micolau, J. Portal","doi":"10.1109/LATW.2012.6261253","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261253","url":null,"abstract":"An oscillator concept used for particle detection and diagnosis is presented. The methodology used to characterize the currents generated by particles is detailed and the results extracted from a DOE analysis are presented.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114861725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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