Low-power design under variation using error prevention and error tolerance (invited paper)

Abstract

This paper presents error tolerance and error prevention methodologies to reduce power dissipation in digital circuits under process variations. For logic circuits, timing error prevention using time-borrowing and clock stretching is discussed as a feasible approach to reduce power dissipation for a target throughput. The natural error tolerance in image processing applications is exploited to reduce power dissipations in Static Random Access Memory (SRAM).