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2012 13th Latin American Test Workshop (LATW)最新文献

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Parametric DC and noise measurements in a unified test & characterization software tool framework 参数直流和噪声测量在一个统一的测试和表征软件工具框架
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261239
José A. Rodríguez, M. Jimenez, William Morales, F. Hou, Lucianne Millan, R. Palomera
{"title":"Parametric DC and noise measurements in a unified test & characterization software tool framework","authors":"José A. Rodríguez, M. Jimenez, William Morales, F. Hou, Lucianne Millan, R. Palomera","doi":"10.1109/LATW.2012.6261239","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261239","url":null,"abstract":"Testing and characterization are fundamental tasks in any semiconductor manufacturing or circuit development activity. These activities call for flexible, yet efficient tools that allow for automated execution. This paper describes the development of an independent Testing Development Environment (TDE) as a platform for designing testing and characterization procedures for use in a production line setting. The proposed platform supports DC, parametric, and noise measurement capabilities in a modular, designer customizable library of testing functions. The platform structure, customization protocols, and I/O formats are discussed, along with the process of populating its function library with procedures for evaluating passive and active devices with diverse requirements and formats. Over four dozen testing procedures have been added to the tool. User-level interactions are used to illustrate the easiness of use and flexibility of this platform.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122989803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low voltage testing for interconnect opens under process variations 在工艺变化情况下进行互连开关的低压测试
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261231
Jesus Moreno, V. Champac, M. Renovell
{"title":"Low voltage testing for interconnect opens under process variations","authors":"Jesus Moreno, V. Champac, M. Renovell","doi":"10.1109/LATW.2012.6261231","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261231","url":null,"abstract":"Advances in test methodologies to deal with subtle behavior of some defects mechanisms as the technology scale are required. Among these interconnect opens are an important defect mechanism that requires detailed knowledge of its physical properties. Furthermore, in nanometer process variability is predominant and considering only nominal value of parameters is not realistic. In this work the detection capability of Low Voltage Testing for interconnect opens, considering process variations, is evaluated using a statistical model. To account for this the Probability of Detection of the defect is obtained. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. The results suggest that using Low Vdd in conjunction with favorable test vectors allow to improve the Probability of Detection of interconnect opens leading to better test quality.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122554199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Platform for automated HW/SW co-verification, testing and simulation of microprocessors 微处理器的自动化硬件/软件协同验证、测试和仿真平台
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261242
A. Simevski, R. Kraemer, M. Krstic
{"title":"Platform for automated HW/SW co-verification, testing and simulation of microprocessors","authors":"A. Simevski, R. Kraemer, M. Krstic","doi":"10.1109/LATW.2012.6261242","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261242","url":null,"abstract":"The high complexity of very deep-submicron Systems-on-Chip makes their verification extremely challenging task. Various methodologies based on traditional simulation, assertion-based verification, formal verification etc. help increase the confidence that a circuit is working according to specification, but in most of the cases an assertion that a circuit is 100% compliant to its specifications is not reachable.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126131754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fast and scalable temperature-driven floorplan design in 3D MPSoCs 在3D mpsoc中快速和可扩展的温度驱动平面图设计
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261245
Ignacio Arnaldo, A. Vincenzi, J. Ayala, J. L. Risco-Martín, J. Hidalgo, M. Ruggiero, David Atienza Alonso
{"title":"Fast and scalable temperature-driven floorplan design in 3D MPSoCs","authors":"Ignacio Arnaldo, A. Vincenzi, J. Ayala, J. L. Risco-Martín, J. Hidalgo, M. Ruggiero, David Atienza Alonso","doi":"10.1109/LATW.2012.6261245","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261245","url":null,"abstract":"Temperature-driven floorplaners have been recently proposed to alleviate the thermal problem in 3D multi-processor systems-on-chip (MPSoC). However, the proposed algorithms fail to provide fast placement of the modules when the complexity and the number of functional units in the stack increases. This paper proposes a fast and scalable CPU-GPU implementation of a multi-objective evolutionary algorithm that performs a thermal optimization of complex 3D MPSoCs, capable of obtaining optimal solutions in a reduced time. A comparative study shows that this work outperforms other proposals and reduces the computational time of the thermal optimization of complex architectures.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125022446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy 基于自适应电校准策略的MEMS对流加速度计可制造性设计
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261237
A. Rekik, F. Azaïs, F. Mailly, P. Nouet
{"title":"Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy","authors":"A. Rekik, F. Azaïs, F. Mailly, P. Nouet","doi":"10.1109/LATW.2012.6261237","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261237","url":null,"abstract":"In this paper, we explore the use of an adaptive electrical calibration strategy in the context of design-for-manufacturing for MEMS convective accelerometers. The calibration principle relies on the adjustment of the heater power level such that sensitivity is set to a given target value. The idea is to define multiple sensitivity targets in order to improve production yield and to insert a criterion on power consumption. Different device binning can then be achieved depending on test limit settings. Results obtained from Monte-Carlo simulation are presented to demonstrate potentialities of the technique.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133869716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Self-optimization of dense wireless sensor networks based on simulated annealing 基于模拟退火的密集无线传感器网络自优化
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261236
A. R. Pinto, A. Cansian, J. M. Machado, C. Montez
{"title":"Self-optimization of dense wireless sensor networks based on simulated annealing","authors":"A. R. Pinto, A. Cansian, J. M. Machado, C. Montez","doi":"10.1109/LATW.2012.6261236","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261236","url":null,"abstract":"Wireless sensor network (WSN) Is a technology that can be used to monitor and actuate on environments in a non-intrusive way. The main difference from WSN and traditional sensor networks is the low dependability of WSN nodes. In this way, WSN solutions are based on a huge number of cheap tiny nodes that can present faults in hardware, software and wireless communication. The deployment of hundreds of nodes can overcome the low dependability of individual nodes, however this strategy introduces a lot of challenges regarding network management, real-time requirements and self-optimization. In this paper we present a simulated annealing approach that self-optimize large scale WSN. Simulation results indicate that our approach can achieve self-optimization characteristics in a dynamic WSN.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123794280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Configurable tool to protect processors against SEE by software-based detection techniques 可配置的工具，以保护处理器对基于软件的检测技术
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261259
E. Chielle, Raul S. Barth, Â. Lapolli, F. Kastensmidt
{"title":"Configurable tool to protect processors against SEE by software-based detection techniques","authors":"E. Chielle, Raul S. Barth, Â. Lapolli, F. Kastensmidt","doi":"10.1109/LATW.2012.6261259","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261259","url":null,"abstract":"This paper presents a tool capable of automatically adding fault detection capabilities in software to protect the processors against transient faults. The tool implements a set of configurable software-based detection techniques over the assembly code of an unprotected program. The developed tool has been validated for two distinct processors: MIPS and LEON3. But it can be extended to other architectures and organizations by changing the configuration files. A fault injection campaign was performed and simulation results show high detection rates to both processors and a small increase in area and runtime.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Mutation operators for concurrent programs in MPI MPI中并发程序的变异算子
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261240
Rodolfo A. Silva, S. Souza, P. L. D. Souza
{"title":"Mutation operators for concurrent programs in MPI","authors":"Rodolfo A. Silva, S. Souza, P. L. D. Souza","doi":"10.1109/LATW.2012.6261240","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261240","url":null,"abstract":"Concurrent Programming became an essential paradigm to reduce the computational time in many application domains. Mutation testing is an important criterion which uses mistakes made by software developers to derive test requirements. To apply this criterion in context of concurrent programs it is necessary to consider the implicit features of these programs, such as: communication, synchronization and non-determinism. Due to the non-determinism, special attention must be given during the mutant behavior analysis. This paper presents a set of mutation operators for concurrent programs in MPI (Message Passing Interface). This mutation operators set was defined based on typical errors of concurrent programs, extracted from literature. An example is presented to illustrate the application of the mutation operators to reveal faults in MPI programs.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127293993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Selective hardening methodology for combinational logic 组合逻辑的选择性强化方法
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261262
S. Pagliarini, L. Naviner, J. Naviner
{"title":"Selective hardening methodology for combinational logic","authors":"S. Pagliarini, L. Naviner, J. Naviner","doi":"10.1109/LATW.2012.6261262","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261262","url":null,"abstract":"Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is based on the SPRA algorithm for calculating logical masking, and it is capable to automatically perform a trade-off between reliability improvements and associated costs, providing a list of the most effective candidates for hardening. The methodology is applied to a set of benchmark circuits using costs extracted from an actual standard cell library. The results then show that the methodology is able to diminish the unreliability of circuits in a cost-effective manner.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126899795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM 研究在SRAM中使用片上传感器来监测NBTI效应
2012 13th Latin American Test Workshop (LATW) Pub Date : 2012-04-10 DOI: 10.1109/LATW.2012.6261238
A. Ceratti, T. Copetti, L. Bolzani, F. Vargas
{"title":"Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM","authors":"A. Ceratti, T. Copetti, L. Bolzani, F. Vargas","doi":"10.1109/LATW.2012.6261238","DOIUrl":"https://doi.org/10.1109/LATW.2012.6261238","url":null,"abstract":"Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena degrading nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI). This paper proposes a new approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. The sensor is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM contents after testing. To prevent OCAS from aging by one side and from dissipating static power by the other side, OCAS circuitry is powered-off during idle periods. SPICE simulations in a 65nm CMOS technology demonstrate the high sensor sensitivity to detect early aging states and so, guarantying high memory reliability. Furthermore, area overhead due to sensor insertion is almost negligible.","PeriodicalId":173735,"journal":{"name":"2012 13th Latin American Test Workshop (LATW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126552948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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