2014 24th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第2页

Effective FPGA debug for high-level synthesis generated circuits 有效的FPGA调试高级合成生成电路

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927498

Jeffrey B. Goeders, S. Wilton

引用次数: 49

A high performance alternating projections image demosaicing hardware 一种高性能交替投影图像去马赛克硬件

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927412

Hasan Azgin, Serkan Yaliman, Ilker Hamzaoglu

引用次数: 5

Accurate power control and monitoring in ZYNQ boards ZYNQ板的精确电源控制和监控

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927415

A. Beldachi, J. Núñez-Yáñez

引用次数: 23

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs 通过动态可重构fpga有效仿真asic中的永久故障

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927478

E. Sánchez, L. Sterpone, Anees Ullah

引用次数: 7

Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation 基于粒子滤波的最大似然估计金融参数估计

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927411

Jinzhe Yang, Binghuan Lin, W. Luk, Terence Nahar

引用次数: 3

Criticality-aware scrubbing mechanism for SRAM-based FPGAs 基于sram的fpga的临界感知擦洗机制

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927476

Rui Santos, Shyamsundar Venkataraman, Anup Das, Akash Kumar

{"title":"Criticality-aware scrubbing mechanism for SRAM-based FPGAs","authors":"Rui Santos, Shyamsundar Venkataraman, Anup Das, Akash Kumar","doi":"10.1109/FPL.2014.6927476","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927476","url":null,"abstract":"Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA. They often do not execute the scrubbing process in the right instant, which minimizes the probability of each task being executed without transient faults. Moreover, these current solutions are not adapted to the tasks' fault-tolerance requirements, since they may not properly protect the most critical tasks in the system. However, if they do it, they waste resources with the less critical tasks. In this paper, a new scrubbing mechanism is proposed. This new approach adapts the scrubbing mechanism to the tasks' execution, by a proper scheduling and according to their criticality. A proposed heuristic finds a feasible scrubbing schedule for each hardware task. Firstly, the minimum scrubbing periods are computed according to the criticality of each implemented hardware task. Secondly, a proper scrubbing schedule following the EDL (Earliest Deadline as Late as possible) algorithm is found, maximizing the reliability of the system. The experimental results show up to 79% improvements on the system reliability, achieved without wasting scrubbing resources.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116286730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Application specific multi-port memory customization in FPGAs fpga中特定于应用程序的多端口存储器定制

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927426

Gorker Alp Malazgirt, Hasan Erdem Yantır, A. Yurdakul, S. Niar

引用次数: 17

FPGA acceleration of SAT/Max-SAT solving using variable-way cache 采用可变路径缓存的FPGA加速SAT/Max-SAT求解

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927405

K. Kanazawa, T. Maruyama

引用次数: 13

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing 具有串行AP-LLR处理的低成本FPGA分层LDPC解码器

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927474

O. Boncalo, A. Amaricai, A. Hera, V. Savin

{"title":"Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing","authors":"O. Boncalo, A. Amaricai, A. Hera, V. Savin","doi":"10.1109/FPL.2014.6927474","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927474","url":null,"abstract":"This paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is based on merging variable and check node processing into one single variable-check node (VCN) unit. Layer message computation is done using a parallel scheme of a number of VCNs equal to the expansion factor of the QC matrix. The proposed architecture is characterized by the serial processing of the a posteriori LLRs by an FPGA specific high frequency VCN unit implementation using ROM memories. In our approach data conversions as well as additions and comparators are replaced by look-up-tables implemented using distributed RAM. In addition to this, other techniques such as: efficient packaging of LLRs messages and check-node message compression as well as the configurable port width of the FPGA's BRAM are used to reduce BRAM block utilization. Throughput increase is achieved by utilizing techniques such as pipelining, parallel processing of multiple VCNs, as well as relatively high working frequency. Implementation results for the WiMAX (1152, 2304) QC irregular LDPC code indicate that the proposed architecture has up to 3x less slices resource utilization and up to 1 order of magnitude less BRAM blocks with respect to other approaches, while maintaining a throughput of several hundreds of Mbps (800 Mbps coded bits). We achieved this without sacrificing flexibility; therefore we can easily adapt our design to accommodate different code rates.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125217956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC 基于fpga的SoC实现神经处理加速器的神经网络仿真模型的硬件转换

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927383

M. Pietras

引用次数: 12