2014 24th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第3页

MAPC: Memory access pattern based controller 基于内存访问模式的控制器

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927397

Tassadaq Hussain, Oscar Palomar, O. Unsal, A. Cristal, E. Ayguadé, M. Valero

引用次数: 7

Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform 加速非均匀快速傅里叶变换的节能重网格结构

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927451

Umer I. Cheema, G. Nash, R. Ansari, A. Khokhar

引用次数: 4

Efficient multi-standard cognitive radios on FPGAs fpga上的高效多标准认知无线电

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927380

T. Pham, Suhaib A. Fahmy, I. Mcloughlin

引用次数: 2

Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures 用于基于tile的混合粒度可重构架构的运行时加速器绑定

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927392

C. Diniz, M. Shafique, S. Bampi, J. Henkel

引用次数: 1

The LEAP FPGA operating system LEAP FPGA操作系统

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1007/978-3-319-26408-0_14

Kermin Fleming, Michael Adler

引用次数: 57

Rapid codesign of a soft vector processor and its compiler 软矢量处理器及其编译器的快速协同设计

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927425

Matthew Naylor, S. Moore

引用次数: 3

Interconnect for commodity FPGA clusters: Standardized or customized? 商用FPGA集群的互连:标准化还是定制?

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927472

A. T. Markettos, P. Fox, S. Moore, A. Moore

引用次数: 15

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring FPGA加速在网络流量监控中的权衡与逐步采用

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927443

Lukás Kekely, V. Pus, Pavel Benácek, J. Korenek

{"title":"Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring","authors":"Lukás Kekely, V. Pus, Pavel Benácek, J. Korenek","doi":"10.1109/FPL.2014.6927443","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927443","url":null,"abstract":"Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security threats.We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. The concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or CycloneV) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100Gb/s flow traffic measurement augmented by a selected application protocol analysis.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128906470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A combination of multi-edge coding and independent coding lines for time-to-digital conversion 多边编码和独立编码线的组合，用于时间到数字的转换

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927382

Dominik Sondej, R. Szplet

引用次数: 1

Scalable parallel architecture for singular value decomposition of large matrices 大矩阵奇异值分解的可扩展并行结构

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927393

Unai Martinez-Corral, Koldo Basterretxea, Raul Finker

{"title":"Scalable parallel architecture for singular value decomposition of large matrices","authors":"Unai Martinez-Corral, Koldo Basterretxea, Raul Finker","doi":"10.1109/FPL.2014.6927393","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927393","url":null,"abstract":"Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications, many of them involving high dimensionality datasets and real-time response. In this paper we describe a scalable parallel processing architecture for accelerating the SVD of large m × n matrices. Based on a linear array of simple processing-units (PUs), the proposed architecture follows a double data-flow paradigm (FIFO memories and a shared-bus) for optimizing the time spent in data transferences. The PUs, which perform elemental column-pair evaluations and rotations, have been designed for an efficient utilization of available FPGA resources and to achieve maximum algorithm speed-ups. The architecture is fully scalable from a two-PU scheme to an arrangement with as many as n/2 PUs. This allows for a trade-off between occupied area and processing acceleration in the final implementation, and permits the SVD processor to be implemented both on low-cost and high-end FPGAs. The system has been prototyped on Spartan-6 and Kintex-7 devices for performance comparison.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122292578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5