Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform

Abstract

This paper proposes a novel FPGA-based accelerator for the memory and compute-intense re-gridding process used in computation of Non-uniform Fast Fourier Transform (NuFFT). The re-gridding process interpolates arbitrary sampled data onto a uniform grid using an interpolation kernel function. This regridding step is considered one of the most time consuming step in entire NuFFT computation. We propose a memory-efficient technique based on the novel use of customizable hardware components such as FPGA block memory in First-In-First-Out (FIFO) configuration, fill-rate based arbiter, distributed RAM and an array of pipelined single precision floating point multipliers and adders. The proposed architecture exhibits high performance over a wide range of configurations and data-sizes. A speed-up of over 9.6 was achieved when compared with existing FPGA-based technique at a 7 times higher MFLOPS per watt. Compared to GPU based technique, over 6 times higher MFLOPS per watts were achieved.