2014 24th International Conference on Field Programmable Logic and Applications (FPL)最新文献_第4页

An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction 一种FPGA硬件加速的树长度间接计算方法，用于系统发育树重建

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927430

Henry Block, T. Maruyama

引用次数: 7

A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs 一种位交错嵌入式汉明方案，用于校正基于sram的fpga的单位和多位干扰

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927385

Shyamsundar Venkataraman, Rui Santos, Anup Das, Akash Kumar

引用次数: 10

Automatic high-level synthesis of multi-threaded hardware accelerators 自动高级合成多线程硬件加速器

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927432

Jens Huthmann, J. Oppermann, A. Koch

引用次数: 13

A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures 适合现代多核和GPU架构的可扩展、串行等效、高质量并行放置方法

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927481

C. Fobel, G. Grewal, D. Stacey

{"title":"A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures","authors":"C. Fobel, G. Grewal, D. Stacey","doi":"10.1109/FPL.2014.6927481","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927481","url":null,"abstract":"Placement and routing run-times continue to dominate the automated FPGA design flow. As the size of FPGA architectures continue to grow exponentially, it remains critical to develop parallel tools for FPGA design where the amount of exposed concurrent work scales with the size of the designs to be synthesized. In this paper, we propose a novel algorithm for parallel placement, based on simulated annealing, where the amount of parallel work directly scales with the size of the net-list to be placed. Our approach concurrently evaluates and conditionally applies very large sets of non-conflicting swaps using common parallel computing primitives, including stream compaction, category reduction, and sort. While our design is suitable for targeting all modern parallel computing platforms, we present results from our implementation which targets NVIDIA's CUDA platform, where we achieve a mean speed-up of 19x over VPR with post-routing critical-path-delay and wire-length quality that matches or exceeds VPR. We believe that this work is an important step towards the development of a scalable, high-quality placement tool.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116550733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model HyPER:一个运行时可重构的架构，用于赫斯顿模型中的蒙特卡罗期权定价

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927458

Christian Brugger, C. D. Schryver, N. Wehn

引用次数: 8

TransPar: Transformation based dynamic Parallelism for low power CGRAs 基于转换的低功耗CGRAs动态并行性

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927485

Syed M. A. H. Jafri, G. Serrano, M. Daneshtalab, Naeem Abbas, A. Hemani, K. Paul, J. Plosila, H. Tenhunen

{"title":"TransPar: Transformation based dynamic Parallelism for low power CGRAs","authors":"Syed M. A. H. Jafri, G. Serrano, M. Daneshtalab, Naeem Abbas, A. Hemani, K. Paul, J. Plosila, H. Tenhunen","doi":"10.1109/FPL.2014.6927485","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927485","url":null,"abstract":"Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer runtime parallelism to reduce energy consumption (by lowering voltage/frequency). To implement the runtime parallelism, CGRAs commonly store multiple compile-time generated implementations of an application (with different degree of parallelism) and select the optimal version at runtime. However, the compile-time binding incurs excessive configuration memory overheads and/or is unable to parallelize an application even when sufficient resources are available. As a solution to this problem, we propose Transformation based dynamic Parallelism (TransPar). TransPar stores only a single implementation and applies a series for transformations to generate the bitstream for the parallel version. In addition, it also allows to displace and/or rotate an application to parallelize in resource constrained scenarios. By storing only a single implementation, TransPar offers significant reductions in configuration memory requirements (up to 73% for the tested applications), compared to state of the art compaction techniques. Simulation and synthesis results, using real applications, reveal that the additional flexibility allows up to 33% energy reduction compared to static memory based parallelism techniques. Gate level analysis reveals that TransPar incurs negligible silicon (0.2% of the platform) and timing (6 additional cycles per application) penalty.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134579507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

High-throughput implementation of a million-point sparse Fourier Transform 百万稀疏傅里叶变换的高吞吐量实现

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927450

Abhinav Agarwal, Haitham Hassanieh, Omid Salehi-Abari, Ezzeldin Hamed, D. Katabi, Arvind

引用次数: 25

Towards dark silicon era in FPGAs using complementary hard logic design 迈向暗硅时代的fpga采用互补硬逻辑设计

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927504

A. Ahari, Behnam Khaleghi, Zahra Ebrahimi, H. Asadi, M. Tahoori

{"title":"Towards dark silicon era in FPGAs using complementary hard logic design","authors":"A. Ahari, Behnam Khaleghi, Zahra Ebrahimi, H. Asadi, M. Tahoori","doi":"10.1109/FPL.2014.6927504","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927504","url":null,"abstract":"While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional Look-Up Table (LUT). Both GRHL cells and LUTs can be power gated and turned off by controlling configuration bits. In the proposed MC, only one cell is active and the others are turned off. Experimental results on MCNC benchmark suite reveal that the proposed architecture reduces the critical path delay, power, and Power Delay Product (PDP) of LBs up to 5.3%, 30.4%, and 28.8% as compared to the equivalent LUT-based architecture.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems PR-HMPSoC:一个通用的部分可重构异构多处理器片上系统，用于基于fpga的动态嵌入式系统

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927492

T. D. A. Nguyen, Akash Kumar

{"title":"PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems","authors":"T. D. A. Nguyen, Akash Kumar","doi":"10.1109/FPL.2014.6927492","DOIUrl":"https://doi.org/10.1109/FPL.2014.6927492","url":null,"abstract":"FPGA-based heterogeneous Multiprocessor Systems-on-Chip (HMPSoCs) are becoming quite popular for high performance embedded systems because of their powerful computational ability and relatively flexible architecture to adapt to unexpected system requirement changes. However, with the insatiable demands of supporting an extensive range of applications beyond the limited resources of FPGA chip and shorter time-to-market, many research works on partially reconfigurable (PR) FPGA architectures have been conducted to fulfill the needs. Those have yet to fully provide a versatile framework to exploit the flexibility of PR such as hardware/software task migration and bitstream relocation; more importantly, the on-chip debug features to access all processors currently loaded in the system are compromised because of the lack of native-support from vendor tools. In this paper, a novel PR-HMPSoC architecture for dynamic FPGA-based embedded system is proposed to provide solutions for all of the above issues. The results from the experimental system consisting of one static Microblaze and three PR Microblaze/hardware accelerators connected by a Network-on-Chip show that the architecture is very promising with just 8% reduction in operating frequency.","PeriodicalId":172795,"journal":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114334173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Experimental multi-FPGA GNSS receiver platform 实验性多fpga GNSS接收机平台

2014 24th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2014-10-20 DOI: 10.1109/FPL.2014.6927399

F. Garzia, A. Rügamer, R. Koch, P. Neumaier, E. Serezhkina, M. Overbeck, G. Rohmer

引用次数: 0