Automatic high-level synthesis of multi-threaded hardware accelerators

Abstract

We describe extending the hardware/software co-compiler Nymble to automatically generate multi-threaded (SIMT) hardware accelerators. In contrast to prior work that simply duplicated complete compute units for each thread, Nymble-MT reuses the actual computation elements, and adds just the required data storage and context switching logic. On the CHStone benchmark suite and a sample configuration of four threads, the prototype can up to quadruple the throughput, but with a chip area just 5% larger than that of a single-threaded accelerator.