2020 IEEE Applied Power Electronics Conference and Exposition (APEC)最新文献

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Conducted EMI Performance of Active Neutral Point Clamped Phase Leg for Dual Active Bridge Converter based DC system 双有源桥式变换器直流系统有源中性点箝位相腿的传导电磁干扰性能
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124272
Saurabh Kumar, G. Gohil
{"title":"Conducted EMI Performance of Active Neutral Point Clamped Phase Leg for Dual Active Bridge Converter based DC system","authors":"Saurabh Kumar, G. Gohil","doi":"10.1109/APEC39645.2020.9124272","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124272","url":null,"abstract":"Neutral Point Clamped (NPC) converter configuration is suitable for operation at Medium Voltage DC (MVDC) level as it allows the use of a higher DC bus voltage than the blocking capability of individual switching devices. The Active NPC (ANPC) configuration offers more flexibility than NPC in terms of control and power loss distribution. NPC/ANPC phase leg aspires to be an ideal candidate for the MVDC side of a Dual Active Bridge (DAB) converter which is used in a wide range of applications requiring bidirectional power flow, voltage matching and soft-switching. Operation under Zero Voltage Switching (ZVS) and the conducted Electromagnetic Interference (EMI) performance of the ANPC converter phase leg is being analyzed in this paper. Based on the analysis, a Printed Circuit Board (PCB) bus-bar has been designed to suppress the high frequency conducted EMI of the system. Minimization of parasitic capacitance from drain to heat sink has also been discussed.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114429036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhancement of Surge-Suppression Performance of a Solid-State Snubber by a SiC Avalanche-Diode 碳化硅雪崩二极管增强固态缓冲器的浪涌抑制性能
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124172
K. Koseki, M. Yamamoto, Yasunori Tanaka
{"title":"Enhancement of Surge-Suppression Performance of a Solid-State Snubber by a SiC Avalanche-Diode","authors":"K. Koseki, M. Yamamoto, Yasunori Tanaka","doi":"10.1109/APEC39645.2020.9124172","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124172","url":null,"abstract":"A solid-state snubber by a silicon carbide (SiC) p-n junction diode has been fabricated to suppress disturbing effect of surge voltage during turn-off transient of semiconductor devices. The operational performance was evaluated experimentally in a step-down DC/DC converter. As a result, it was found that a wiring inductance between the switching element (metal oxide semiconductor field effect transistor, MOSFET) and the solid-state snubber limits the surge-suppression performance. A co-pack, in which the MOSFET and the solid-state snubber are implemented on a same substrate contiguously, was developed to mitigates the effect by the parasitic inductance. The drastic enhancement in the surge-suppression performance in the co-pack configuration was obtained.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115020335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Improved Control Strategy for A Single-Phase Non-Isolated Photovoltaic Grid-Tied Inverter 一种改进的单相非隔离光伏并网逆变器控制策略
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124048
Jianbo Jiang, S. Pan, L. Xie, Weiwen Zeng, Jinwu Gong, X. Zha
{"title":"An Improved Control Strategy for A Single-Phase Non-Isolated Photovoltaic Grid-Tied Inverter","authors":"Jianbo Jiang, S. Pan, L. Xie, Weiwen Zeng, Jinwu Gong, X. Zha","doi":"10.1109/APEC39645.2020.9124048","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124048","url":null,"abstract":"Single-phase non-isolated inverters are widely utilized in distributed photovoltaic grid-connected applications. However, single-phase full-bridge inverters often suffer from the leakage current and the double-frequency power oscillation. A single-phase non-isolated inverter is investigated in this paper, which can handle the problem of the leakage current and the double-frequency power oscillation simultaneously. The presented inverter allows the neutral line of the AC grid directly connected to the negative terminal of the PV panel so that the leakage current is completely eliminated. Besides, based on a power decoupling method, the double-frequency power oscillation on the DC side can be suppressed without additional passive components. The state space model of the inverter is established and the influence of each parameter on its stability is analyzed in detail, and then an improved control strategy is proposed to reduce the inductance of the internal inductor. The effectiveness of the improved control strategy is verified by simulation and experimental results.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115033621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Transformer-less Hybrid PV Inverter with Integrated Battery Energy Storage 集成电池储能的无变压器混合光伏逆变器
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124113
Fahad M. Alhuwaishel, P. Enjeti
{"title":"A Transformer-less Hybrid PV Inverter with Integrated Battery Energy Storage","authors":"Fahad M. Alhuwaishel, P. Enjeti","doi":"10.1109/APEC39645.2020.9124113","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124113","url":null,"abstract":"In this paper a transformer-less hybrid PV inverter with integrated battery energy storage is proposed. The proposed converter integrates both solar PV and battery sources with the ability to control for maximum power transfer as well as control the charge discharge functions of a battery energy storage system. The proposed control employs a single current and single voltage sensor with perturb and observe based method to achieve maximum solar power and battery state of charge control. The proposed interleaved modular multilevel converter boosts the dc link voltage to suitable value to enable transformer-less interface to the electric commercial utility grid. It is shown that ZVS operation will yield higher conversion efficiency. Simulation results validate the concept over a wide operation range. Preliminary experimental results are discussed.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116908232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Medium Power SiC Module with Integrated Active Snubber for Lowest Switching Losses 一种集成有源缓冲器的中功率SiC模块,可实现最低开关损耗
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124178
M. Schlüter, A. Uhlemann, M. Pfost
{"title":"A Medium Power SiC Module with Integrated Active Snubber for Lowest Switching Losses","authors":"M. Schlüter, A. Uhlemann, M. Pfost","doi":"10.1109/APEC39645.2020.9124178","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124178","url":null,"abstract":"Better EMI performance and lower switching losses are important goals in power electronics. Since several years, wide-bandgap materials are subject of research, providing faster switching speeds and thus lower switching losses. However, fast transistors tend to oscillate due to stray inductance and parasitic capacitances. Furthermore, a high stray inductance leads to a high voltage overshoot at turn-off. For those reasons, a small stray inductance is essential for low EMI and low switching losses. A major difficulty during the development of a power electronic system is that the stray inductance is distributed over several parts, e.g. the DC-link capacitor, the connection, and the power module. Thus, achieving a low stray inductance is challenging. To alleviate that is the use of a snubber circuit, which, however, may lead to even higher overall losses. In this paper, a medium power SiC-MOSFET module is presented with an integrated active snubber that makes use of the energy in the stray inductance. It is compared with two other topologies, a standard halfbridge and a halfbridge with integrated DC snubber. The three topologies are tested in identical setups for hard-switching operation at 600V and 350A, all with similar DBC layout. It is shown that the voltage overshoot, the tendency to oscillate, and the system losses are strongly decreased due to the active snubber.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116940006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Balancing control of paralleled full-bridge converters in high-current gradient amplifiers for MRI applications MRI大电流梯度放大器并联全桥变换器的平衡控制
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124390
Misha Kumar, L. Huber, He Huang, Zhiyu Shen, Hongyuan Jin
{"title":"Balancing control of paralleled full-bridge converters in high-current gradient amplifiers for MRI applications","authors":"Misha Kumar, L. Huber, He Huang, Zhiyu Shen, Hongyuan Jin","doi":"10.1109/APEC39645.2020.9124390","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124390","url":null,"abstract":"To achieve a high current (>500 A) in gradient amplifiers, two full-bridge (FB) converters are paralleled such that each FB converter carries equal share of the gradient-coil current. However, achieving equal current sharing is very challenging because it requires perfect synchronization between the gate pulses of the paralleled FB converters. To achieve equal current sharing, coupled inductors with a large value of magnetizing inductance LM can be added between the paralleled FB converters. However, a large value of LM requires large volume of the coupled inductors. In this paper, to achieve equal current sharing, a combined hardware-software approach is proposed in which, coupled inductors with a small value of LM are used along with a balancing control. Detailed analysis of causes of unequal current sharing between paralleled FB converters is provided. In addition, digital control of two paralleled FB converters with the proposed balancing control is described in details. Finally, simulation and experimental results obtained without and with the proposed balancing control for two paralleled FB converters with 75-A and 400-A maximum gradient-coil currents are presented.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117306142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modelling and Experimental Evaluation of Ideal Transformer Algorithm Interface for Power Hardware in the Loop Architecture 电力硬件环路结构理想变压器算法接口的建模与实验评价
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124046
Mandip Pokharel, Carl Ngai Man Ho
{"title":"Modelling and Experimental Evaluation of Ideal Transformer Algorithm Interface for Power Hardware in the Loop Architecture","authors":"Mandip Pokharel, Carl Ngai Man Ho","doi":"10.1109/APEC39645.2020.9124046","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124046","url":null,"abstract":"Interface devices are crucial to achieving Power Hardware in the Loop (PHIL) configuration. It is the interface that separates PHIL implementation with its real counterpart. This inclusion of interface at power decoupling point has raised the concern of stability and accuracy among researchers. It is therefore essential to study the effect of interface if the PHIL system is to be entirely understood. Ideal Transformer Algorithm (ITA) is one of the widely used interfacing method for PHIL due to its implementation simplicity. Moreover, the existing models of ITA relies only on the theoretical model developed. This work constitutes the study and development of accurate mathematical model of individual interface devices in ITA. Further, this paper uses a frequency sweep approach to determine the responses from the actual system consisting of a Real Time Digital Simulator (RTDS). This experimentally obtained frequency response is then compared with model response to test the accuracy of the developed model. This paper therefore bridges the existing gap in interface model by experimentally verifying the developed model. The theoretical and experimental model are well within agreement to further the studies in PHIL.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116182394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Control Scheme to Mitigate the Dead-Time Effects in a Wireless Power Transfer System 一种减轻无线电力传输系统死区效应的控制方案
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124590
Utkarsh D. Kavimandan, V. Galigekere, O. Onar, B. Ozpineci, S. Mahajan
{"title":"A Control Scheme to Mitigate the Dead-Time Effects in a Wireless Power Transfer System","authors":"Utkarsh D. Kavimandan, V. Galigekere, O. Onar, B. Ozpineci, S. Mahajan","doi":"10.1109/APEC39645.2020.9124590","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124590","url":null,"abstract":"In practice, a dead-time is always provided between the complementary switching instances of the inverter phase-leg devices. At higher operating frequencies, the dead-time issues in wireless power transfer (WPT) systems become critical, especially as the power level increases. In certain operating conditions, the dead-time effect in wireless power transfer system affects the switching characteristics. Consequently, the switching losses in the power semiconductor devices increase and also impact the efficiency of the overall system. In this paper, a simple control scheme is proposed to eliminate the dead-time effect (or voltage polarity reversal) in the WPT inverter. The proposed control scheme monitors the inverter output voltage, and the switching frequency is auto-tuned to eliminate the undesired switching instances in the inverter voltage. The proposed control scheme is validated using the closed-loop simulations in PLECS, and the experimental results on a 5.6 kW WPT prototype are also presented. After eliminating the voltage-polarity-reversal at the inverter output, the inverter losses were reduced by ∼40%, and the overall system losses were reduced by ∼17%.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116452307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A New High Step-Up DC-DC Topology with Zero DC Magnetizing Inductance Current and Continuous Input Current 具有零直流磁化电感电流和连续输入电流的新型高升压DC-DC拓扑结构
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124151
M. Mahmoudi, A. Ajami, E. Babaei, Nima Abdolmaleki, Caisheng Wang
{"title":"A New High Step-Up DC-DC Topology with Zero DC Magnetizing Inductance Current and Continuous Input Current","authors":"M. Mahmoudi, A. Ajami, E. Babaei, Nima Abdolmaleki, Caisheng Wang","doi":"10.1109/APEC39645.2020.9124151","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124151","url":null,"abstract":"A new high-voltage-gain non-isolated dc-dc topology for applications in renewable energies is proposed. A coupled inductor with three windings is used to increase the proposed topology voltage gain. In addition to increasing the voltage gain, the proposed topology also has other prominent features including continuous input current and zero dc magnetizing inductance current, which reduces the losses and size of coupled inductor core. Furthermore, the continuous input current guarantees a low-volume input filter, which is essential for renewable energy applications. The leakage inductor stored energy is recycled via the diode and capacitor and transferred to the converter output for increasing the efficiency and reducing voltage stresses on the converter components.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An evaluation of the failures in resonant topologies due to the body diode and the role of fast diode MOSFET 对本体二极管和快速二极管MOSFET在谐振拓扑中所起的作用进行了评估
2020 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2020-03-01 DOI: 10.1109/APEC39645.2020.9124541
Domenico Nardo, Alfio Scuto, S. Buonomo
{"title":"An evaluation of the failures in resonant topologies due to the body diode and the role of fast diode MOSFET","authors":"Domenico Nardo, Alfio Scuto, S. Buonomo","doi":"10.1109/APEC39645.2020.9124541","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124541","url":null,"abstract":"The aim of this paper is to evaluate and understand the failure mechanism due to reverse recovery of the intrinsic body diode of the Super Junction MOSFET in terms of physical processes both inside the device and at the converter level. Nowadays, higher reliability and theoretically failure free systems are in high demand in order to maintain service continuity in typical telecom or server applications. The topologies under analysis in this paper are the half bridge resonant converter (HB LLC) and the full bridge resonant converter (FBLLC). Moreover, a solution for this problem based on the fast recovery diode SJ MOSFET based on MDmesh™ technology from STMicroelectronics was proposed.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124043402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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