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High integrity multi-core modelling for future systems (HI-MCM) 面向未来系统的高完整性多核建模(HI-MCM)
2015 Forum on Specification and Design Languages (FDL) Pub Date : 1900-01-01 DOI: 10.1109/fdl.2015.7306357
{"title":"High integrity multi-core modelling for future systems (HI-MCM)","authors":"","doi":"10.1109/fdl.2015.7306357","DOIUrl":"https://doi.org/10.1109/fdl.2015.7306357","url":null,"abstract":"Modern embedded applications already integrate a multitude of functionalities with potentially different criticality levels into a single system. Driven by the availability of embedded multi-core System-on-Chips, this trend is expected to grow in the near future. Without appropriate preconditions, the integration of mixed-criticality subsystems can lead to a significant and potentially unacceptable increase of engineering and certification costs.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132837368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Correctness 设计与正确性
2015 Forum on Specification and Design Languages (FDL) Pub Date : 1900-01-01 DOI: 10.1109/fdl.2015.7306353
D. Stoffel
{"title":"Design and Correctness","authors":"D. Stoffel","doi":"10.1109/fdl.2015.7306353","DOIUrl":"https://doi.org/10.1109/fdl.2015.7306353","url":null,"abstract":"This session presents a domain-specific language for high-level synthesis of hardware for FPGA platforms and describes its memory management for pipelined target architectures. It also presents a methodology to construct test sequences starting from PSL assertions and design under test written in VHDL using VSYML and SyntHorus tools. Finally it presents a top-down design flow to refine an architecture level description of a system into an RTL implementation, while refining operation properties concurrently.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"46 25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122135427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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