2015 Forum on Specification and Design Languages (FDL)最新文献

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Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning 基于多核分区的符合IEC-61508标准的混合临界系统的时间独立性验证
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306359
Asier Larrucea, Irune Agirre, C. F. Nicolás, Jon Pérez, M. Azkarate-askasua, T. Trapman
{"title":"Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning","authors":"Asier Larrucea, Irune Agirre, C. F. Nicolás, Jon Pérez, M. Azkarate-askasua, T. Trapman","doi":"10.1109/FDL.2015.7306359","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306359","url":null,"abstract":"The transition from conventional federated embedded system architectures to mixed-criticality integrated multicore architectures provides benefits in terms of cost, size, weight, scalability and reliability. As a consequence, integrated mixedcriticality solutions are an objective for many embedded systems developers, although the challenges related with the safety certification of multicore approaches may hinder their adoption. Among many other stringent requirements, the safety standards demand to prove that the mixed-criticality systems are free of interferences, thus ensuring the spatial and temporal interdependence among applications. This paper contributes with a measured based temporal independence validation of a partitioned multicore mixed-criticality system.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Conservative behavioural modelling in systemc-AMS 系统- ams中的保守行为模型
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306361
S. Vinco, M. Lora, Mark Zwolinski
{"title":"Conservative behavioural modelling in systemc-AMS","authors":"S. Vinco, M. Lora, Mark Zwolinski","doi":"10.1109/FDL.2015.7306361","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306361","url":null,"abstract":"SystemC has recently been extended with the Analogue and Mixed Signal (AMS) library, with the ultimate goal of providing simulation support to analogue electronics and continuous time behaviours. SystemC-AMS allows modelling of systems that are either conservative and extremely low level or continuous time and behavioural, which is limited compared to other AMS HDLs. This work faces up this challenge, by extending SystemCAMS support to a new level of abstraction, called Analogue Behavioural Modelling (ABM), covering models that are both behavioural and conservative. This leads to a methodology that uses SystemC-AMS constructs in a novel way. Full automation of the methodology allows proof of its effectiveness both in terms of accuracy and simulation performance, and application of the overall approach to a complex industrial Micro Electro- Mechanical System (MEMS) case study. The effectiveness of the proposed approach is further highlighted in the context of virtual platforms for smart systems, as adopting a C++-based language for MEMS simulation reduces the simulation time by about 2x, thus enhancing the design and integration flow.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129903578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Enabler-based synchronizer model for clock domain crossing static verification 基于使能器的时钟域跨静态验证同步器模型
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306080
M. Kebaili, K. Morin-Allory, Jean-Christophe Brignone, D. Borrione
{"title":"Enabler-based synchronizer model for clock domain crossing static verification","authors":"M. Kebaili, K. Morin-Allory, Jean-Christophe Brignone, D. Borrione","doi":"10.1109/FDL.2015.7306080","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306080","url":null,"abstract":"In the context of industrial size circuits, the interconnection of many blocks from many sources lead to globally asynchronous locally synchronous designs. The transmission of information between clock domains requires complex synchronizers, the correctness of which must be thoroughly verified. Current EDA tools are able to recognize predefined synchronizing modules, but fail to identify custom synchronizers. This paper presents a new model and a set of properties to automatically extract synchronizers in a flat design, and formally verify the correctness of the implemented synchronization protocol.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131615192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
From MARTE models to initial implementations 从MARTE模型到初始实现
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306082
F. Herrera, Kim Gruettner
{"title":"From MARTE models to initial implementations","authors":"F. Herrera, Kim Gruettner","doi":"10.1109/FDL.2015.7306082","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306082","url":null,"abstract":"This session presents a proposal of elements for the specialization of the UML profile for MARTE dedicated to networks and distributed embedded systems. It also presents a model-based approach to the problem of dynamically reprogramming an FPGA. By using model-based methods, characterized by high-level specifications, and automated code generation, developers are protected from worrying about low-level and vendor-specific details required for FPGA reprogramming.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126911127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temporal decoupling with error-bounded predictive quantum control 误差有界预测量子控制的时间解耦
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306358
G. Glaeser, Gregor Nitsche, E. Hennig
{"title":"Temporal decoupling with error-bounded predictive quantum control","authors":"G. Glaeser, Gregor Nitsche, E. Hennig","doi":"10.1109/FDL.2015.7306358","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306358","url":null,"abstract":"Virtual prototyping of integrated mixed-signal smart-sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in combination with a cycle-count accurate temporal decoupling approach to simulate digital components and firmware code execution at high speed while preserving clock cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming communication events. These methods fail in case of non-deterministic, asynchronous events resulting in a possibly invalid simulation result. In this paper, we propose an extension of this method to the case of asynchronous events generated by blackbox sources from which a-priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency and/or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. For an example smart-sensor system model, we show that quasi-periodic events that trigger activities in temporally decoupled processes are handled accurately after the predictor has settled.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130027623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A methodology for inserting clock-management strategies in transaction-level models of systemon- chips 在系统芯片的事务级模型中插入时钟管理策略的方法
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306088
H. Affes, M. Auguin, F. Verdier, A. Pegatoquet
{"title":"A methodology for inserting clock-management strategies in transaction-level models of systemon- chips","authors":"H. Affes, M. Auguin, F. Verdier, A. Pegatoquet","doi":"10.1109/FDL.2015.7306088","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306088","url":null,"abstract":"Due to the ever-increasing demands on energy efficiency, designers are struggling to construct efficient and correct power management strategies for complex System-on- Chips (SoCs). The validation of an efficient power intent for a SoC is challenging and should be considered at early stage of the electronic system-level (ESL) design flow. To tackle this issue, we propose a high-level modeling approach on top of SystemC/TLM standard allowing the control structure of a power intent to be described in relationship with a functional transaction-level model (TLM) of a SoC. We consider a separation of concern approach in order to make easier the exploration of power intents and the optimization of power consumption. In this paper, the focus is set on an abstract clock intent model through a generic library and a modeling methodology allowing the development of a power management strategy on top of a functional SystemC-TLM model of a virtual prototype. A case study is used to demonstrate by simulation experiments the efficiency of this approach illustrating its capability to analyze effects of power management on performance and power consumption.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122818468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
WiSeBat: accurate energy benchmarking of wireless sensor networks WiSeBat:无线传感器网络准确的能量基准
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306084
Quentin Bramas, Wilfried Dron, Mariem Ben Fadhl, K. Hachicha, P. Garda, S. Tixeuil
{"title":"WiSeBat: accurate energy benchmarking of wireless sensor networks","authors":"Quentin Bramas, Wilfried Dron, Mariem Ben Fadhl, K. Hachicha, P. Garda, S. Tixeuil","doi":"10.1109/FDL.2015.7306084","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306084","url":null,"abstract":"Recent applications of Wireless Sensor Network require small yet sustainable battery-powered devices. As a consequence, it becomes crucial to accurately and efficiently compute a node's power consumption in order to estimate its lifetime. Existing wireless network simulators either implement simplistic energy consumption and battery models, or very complex and general ones that hinders scalability. In this paper, we (i) present WiSeBat, a module to estimate devices lifetime using realistic energy consumption and battery models, that has specially been optimized for wireless sensor network simulations. We then (ii) validate it through real measurements. Finally, we used it (iii) to compare wireless sensor lifetime in several realistic scenarios. Firstly, we review existing techniques to simulate a battery and discuss what behaviors are important to get realistic and fast simulations. We then propose simulator-independent models for the battery and for the energy consumption of sensors, and implement this model in the WSNet simulator. Secondly, we compare measured and simulated lifetimes of sensors. On the one hand, our experiments show that our models provide an 86 - 96% accurate lifetime estimation. On the other hand, the previous default WSNet models overestimate lifetime by more than 2600%. Once validated, we used our approach to benchmark the energy consumption of different protocol stacks of wireless sensor networks, under different scenarios. These simulations match well-known results in simple scenarios, as we demonstrate better performance of ContikiMAC over X-MAC. They also provide an accurate comparison of sensor lifetime in more complex scenarios.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134323922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling power consumption at system-level for design of power integrity-aware AMS-circuits 基于功率完整性感知的ams电路的系统级功耗建模
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306087
Xiao Pan, Javier Moreno Molina, C. Grimm
{"title":"Modeling power consumption at system-level for design of power integrity-aware AMS-circuits","authors":"Xiao Pan, Javier Moreno Molina, C. Grimm","doi":"10.1109/FDL.2015.7306087","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306087","url":null,"abstract":"Among many challenges in designing reliable integrated circuits and embedded systems, the power integrity (PI-) issue is a particularly critical one. Researches and CAD tools have been carried out in the last decades. However, all of them address the problem from a circuit-level perspective. Moreover, the PIproblem cannot be completely verified until layout, the final stage of the design phase. In this paper we propose a new approach to model power consumption that allows PI-simulation at the system level of abstraction, by extending the state-machine based power estimation method. For this purpose, we model power consumption in power states which also includes a statistical model, and in state-transitions modeled by transfer function. The proposed approach is implemented as part of a simulation framework, which uses SystemC-AMS, and is applied on a battery management IC design.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133694361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Standard compliant co-simulation models for verification of automotive embedded systems 汽车嵌入式系统验证的标准兼容联合仿真模型
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306083
M. Krammer, H. Martin, Zoran Radmilovic, S. Erker, Michael Karner
{"title":"Standard compliant co-simulation models for verification of automotive embedded systems","authors":"M. Krammer, H. Martin, Zoran Radmilovic, S. Erker, Michael Karner","doi":"10.1109/FDL.2015.7306083","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306083","url":null,"abstract":"The functional mockup interface (FMI) is a tool independent standard to support model exchange and cosimulation, as intended by the automotive industry to unify the exchange of simulation models between suppliers and OEMs. The standard defines functional mockup units (FMU) as components which implement the FMI. The creation and exchange of simulation models with customers and suppliers across the automotive supply chain is highly beneficial: In order to support early phases of development (requirement formulation, creation of executable specifications, and rapid prototyping) the creation of FMUs for co-simulation is reasonable. In this paper, we propose a structured method for generation of FMUs for co-simulation which are versatile, highly transportable and fast simulating. We show how to compile FMUs based on SystemC and SystemCAMS, representing digital as well as analog and mixed signal electric and electronic systems. This tool-independent method allows inclusion of existing simulation models with only minimal adaptations. Additionally, no modifications of the standardized libraries are necessary with the outlined approach. The resulting FMUs allow convenient exchange and fast co-simulation of automotive systems, as they may be integrated by any FMI compatible master tool. An automotive battery system use case is shown to highlight these advantages and to demonstrate the simulation performance of the resulting FMUs.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123940697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Extensions to the UML profile for MARTE for distributed embedded systems 用于分布式嵌入式系统的MARTE UML概要文件的扩展
2015 Forum on Specification and Design Languages (FDL) Pub Date : 2015-11-12 DOI: 10.1109/FDL.2015.7306092
E. Ebeid, J. L. M. Pasaje, D. Quaglia, F. Fummi
{"title":"Extensions to the UML profile for MARTE for distributed embedded systems","authors":"E. Ebeid, J. L. M. Pasaje, D. Quaglia, F. Fummi","doi":"10.1109/FDL.2015.7306092","DOIUrl":"https://doi.org/10.1109/FDL.2015.7306092","url":null,"abstract":"The design of distributed embedded systems is a challenging task that requires raising the level of abstraction to handle the different involved concerns. In particular, standard modeling languages and precise semantics specification are necessary to address the networking-related aspects at a high level of abstraction. The Unified Modeling Language (UML) and its MARTE profile are valid formalisms to model real-time embedded systems but they lack precise modeling elements when addressing applications and platforms forming distributed embedded systems. In this work, we formalize a coherent set of modeling elements for the design and deployment of distributed embedded systems. A novel UML profile for networking is proposed as a semantic and syntactic extension to the UML Profile for MARTE: The Network Profile.","PeriodicalId":171448,"journal":{"name":"2015 Forum on Specification and Design Languages (FDL)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115283210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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