发布求助
文献互助 智能选刊 最新文献

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)最新文献

筛选
英文 中文
New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements 微波/射频集成电路非线性行为建模的新技术来自仿真和非线性微波测量
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775856
D. Root, J. Wood, N. Tufillaro
{"title":"New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements","authors":"D. Root, J. Wood, N. Tufillaro","doi":"10.1145/775832.775856","DOIUrl":"https://doi.org/10.1145/775832.775856","url":null,"abstract":"This paper compares and contrasts recent nonlinear behavioral modeling techniques designed for microwave and RFIC application which arise in radio and communication systems, and in the design of broad-band nonlinear components used for microwave instrumentation. These techniques include dynamic neural networks and nonlinear time series models in the time-domain, nonlinear describing functions in the frequency domain, and envelope-based methods in mixed time and frequency domains. Approaches to generating these models from both simulation and nonlinear microwave measurements are reviewed.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132435155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Formal verification - prove it or pitch it 正式的验证——证明或推销它
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.776013
Rajesh K. Gupta, S. Rawat, S. Shukla, B. Bailey, D. Beece, M. Fujita, C. Pixley, J. O'Leary, F. Somenzi
{"title":"Formal verification - prove it or pitch it","authors":"Rajesh K. Gupta, S. Rawat, S. Shukla, B. Bailey, D. Beece, M. Fujita, C. Pixley, J. O'Leary, F. Somenzi","doi":"10.1145/775832.776013","DOIUrl":"https://doi.org/10.1145/775832.776013","url":null,"abstract":"Despite a number of solid advances in simulation and verification techniques over the last twenty years, semiconductor chip designs continue to see large increases in the cost of verification - both in terms of human resources and time. Most of these increases are due to the growing size and complexity of the chip designs. Many of these designs are complete systems in their own right thus enlarging the scope of the verification problem. Formal verification has held out the most promise for reducing the magnitude of the verification task. Indeed, most major microprocessor teams - at IBM, Intel and Motorola - have routinely hosted formal verification experts since the early '90s. ASIC vendors and their tool providers have been closely following these developments into a number of initiatives and new startup companies driven by that very promise of formal verification. Despite these developments, simulation continues to be the final source of signoff - if not confidence - in chip tapeouts. Why is this so? Formal verification is an important technology to be left at the margins of the validation task. Will formal verification eliminate or limit unit level verification and provide the necessary glue for a realistic validation flow? Will the testbenches be replaced by constraints and assertions? Can validation effort be reused? This panel will explore the issues related to building practical validation flows, and the technologies that the designer community can realistically look forward to materializing in their lifetimes.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Random walks in a supply network 供应网络中的随机漫步
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1109/DAC.2003.1218831
Haifeng Qian, S. Nassif, S. Sapatnekar
{"title":"Random walks in a supply network","authors":"Haifeng Qian, S. Nassif, S. Sapatnekar","doi":"10.1109/DAC.2003.1218831","DOIUrl":"https://doi.org/10.1109/DAC.2003.1218831","url":null,"abstract":"This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transient analysis. The method has the desirable property of localizing computation, so that it shows massive benefits over conventional methods when only a small part of the grid is to be analyzed (for example, when the effects of small changes to the grid are to be examined). Even for the full analysis of the grid, experimental results show tat the method is faster than existing approaches and has an acceptable error margin. This method has been applied to test circuits of up to 2.3M nodes. For example, for a circuit with 70K nodes, the solution time for a single node was 0.42 sec and the complete solution was obtained in 17.6 sec.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122148431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 159
On-chip logic minimization 片上逻辑最小化
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775918
Roman L. Lysecky, F. Vahid
{"title":"On-chip logic minimization","authors":"Roman L. Lysecky, F. Vahid","doi":"10.1145/775832.775918","DOIUrl":"https://doi.org/10.1145/775832.775918","url":null,"abstract":"While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such as Internet Protocol routing table and network access control list reduction, require logic minimization during the application's runtime, and hence could benefit from minimization executing on-chip alongside the application. On-chip minimization can even enable dynamic hardware/software partitioning. We discuss requirements of on-chip logic minimization, and present our new on-chip logic minimization tool, ROCM. We compare with the well-known Espresso logic minimizer and show that ROCM is 10 times smaller, executes 10-20 times faster, and uses 3 times less data memory, with a mere 2% quality penalty, for the routing table and access control list applications. We show that ROCM solves real-sized problems on an ARM7 embedded processor in just seconds.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126046522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Power grid reduction based on algebraic multigrid principles 基于代数多重网格原理的电网约简
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1109/DAC.2003.1218840
Haihua Su, E. Acar, S. Nassif
{"title":"Power grid reduction based on algebraic multigrid principles","authors":"Haihua Su, E. Acar, S. Nassif","doi":"10.1109/DAC.2003.1218840","DOIUrl":"https://doi.org/10.1109/DAC.2003.1218840","url":null,"abstract":"With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, making noise analysis and verification challenging in terms of both run time and memory. We propose a power grid reduction scheme based on algebraic multigrid principles, in which the coarser-level grid and the restriction operators are constructed automatically from the circuit matrices. This method is suitable for large-scale power grid transient and AC analysis. Experimental results show an order of magnitude speed up over flat analysis in addition to practical tradeoffs for accuracy, CPU time and memory usage.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123886892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
Improved indexing for cache miss reduction in embedded systems 改进了在嵌入式系统中减少缓存丢失的索引
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.776052
T. Givargis
{"title":"Improved indexing for cache miss reduction in embedded systems","authors":"T. Givargis","doi":"10.1145/775832.776052","DOIUrl":"https://doi.org/10.1145/775832.776052","url":null,"abstract":"The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory address bus consists of the K least significant bits, where K=log/sub 2/(D) and D is the depth of the cache. However, in devices where the application set is known and characterized (e.g., systems that execute a fixed application set) there is an opportunity to improve cache performance by choosing an optimal set of bits used as index into the cache. This technique does not add any overhead in terms of area or delay. We give an efficient heuristic algorithm for selecting K index bits for improved cache performance. We show the feasibility of our algorithm by applying it to a large number of embedded system applications as well as the integer SPEC CPU 2000 benchmarks.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121671074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Behavioral consistency of C and Verilog programs using bounded model checking 使用有界模型检查的C和Verilog程序的行为一致性
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775928
E. Clarke, D. Kroening, K. Yorav
{"title":"Behavioral consistency of C and Verilog programs using bounded model checking","authors":"E. Clarke, D. Kroening, K. Yorav","doi":"10.1145/775832.775928","DOIUrl":"https://doi.org/10.1145/775832.775928","url":null,"abstract":"We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program are unwound and translated into a formula that represents behavioral consistency. The formula is then checked using a SAT solver. We are able to translate C programs that include side effects, pointers, dynamic memory allocation, and loops with conditions that cannot be evaluated statically. We describe experimental results on various reactive circuits and programs, including a small processor given in Verilog and its Instruction Set Architecture given in ANSI-C.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122752445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 304
Application of design patterns for hardware design 设计模式在硬件设计中的应用
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775847
Robertas Damaševičius, G. Majauskas, V. Stuikys
{"title":"Application of design patterns for hardware design","authors":"Robertas Damaševičius, G. Majauskas, V. Stuikys","doi":"10.1145/775832.775847","DOIUrl":"https://doi.org/10.1145/775832.775847","url":null,"abstract":"Design pattersn, which encapsulate common solutions to the recurring design problems, have contributed to the increased reuse, quality and productivity in software design. We argue that hardware design pattern could be used for customizing and integrating the Intellectual Property (IP) components into System-on-Chip designs. We formulate the role of design patterns in HW design, and describe their implementation using metaprogramming. We propose a Wrapper design pattern for adapting the behavior of the soft IPs, and demonstrate its application to the communication interface synthesis.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115692559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Crosstalk noise in FPGAs fpga中的串扰噪声
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.776069
Y. Ran, M. Marek-Sadowska
{"title":"Crosstalk noise in FPGAs","authors":"Y. Ran, M. Marek-Sadowska","doi":"10.1145/775832.776069","DOIUrl":"https://doi.org/10.1145/775832.776069","url":null,"abstract":"In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem affecting circuit reliability. Even though FPGAs are more immune to crosstalk noise than their ASIC counterparts manufactured in the same technological process, we have reached the point where FPGAs have become affected by crosstalk as well. Because FPGAs have regular interconnect structures, crosstalk noise can be more easily controlled. In this paper, we investigate the crosstalk noise in FPGAs and propose new strategies to reduce its impact on delay. Our methods can reduce crosstalk noise by statistically significant amounts with no penalty in performance, power, or area.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Data communication estimation and reduction for reconfigurable systems 可重构系统的数据通信估计与缩减
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775987
A. Kaplan, P. Brisk, R. Kastner
{"title":"Data communication estimation and reduction for reconfigurable systems","authors":"A. Kaplan, P. Brisk, R. Kastner","doi":"10.1145/775832.775987","DOIUrl":"https://doi.org/10.1145/775832.775987","url":null,"abstract":"Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable device. This paper describes methods for synthesizing the internal representation of a compiler into a hardware description language in order to program reconfigurable hardware devices. We demonstrate the usefulness of static single assignment (SSA) in reducing the amount of data communication in the hardware. However, the placement of /spl Phi/-nodes by current SSA algorithms is not optimal in terms of minimizing data communication. We propose a new algorithm which optimally places /spl Phi/-nodes, further decreasing area and communication latency. Our algorithm reduces the data communication (measured as total edge weight in a control data flow graph) by as much as 20% for some applications as compared to the best-known SSA algorithm - the pruned algorithm. We also describe future modifications to our model that should increase the effectiveness of our methods.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126863500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信