Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)最新文献

SAT-based unbounded symbolic model checking 基于sat的无界符号模型检验

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2005-01-24 DOI: 10.1109/DAC.2003.1219136

Hyeong-Ju Kang, I. Park

引用次数: 34

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL 自偏置高带宽低抖动1到4096倍频时钟发生器锁相环

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-10-27 DOI: 10.1145/775832.776006

J. Maneatis, Jaeha Kim, Iain McClatchie, J. Maxey, Manjusha Shankaradas

引用次数: 103

Improvements in functional simulation addressing challenges in large, distributed industry projects 功能模拟的改进，解决了大型分布式工业项目中的挑战

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775836

Klaus-Dieter Schubert

引用次数: 7

Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction Verilog HDL，由PLI提供支持:在所有抽象级别上描述和建模异步电路的合适框架

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775917

Arash Saifhashemi, H. Pedram

引用次数: 50

Manipulation and characterization of molecular scale components 分子尺度组分的操作和表征

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775902

I. Amlani, Ruth Zhang, J. Tresek, L. Nagahara, R. Tsui

引用次数: 3

Analog and RF circuit macromodels for system-level analysis 模拟和射频电路宏模型的系统级分析

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1109/DAC.2003.1219048

Xin Li, Peng Li, Yang Xu, L. Pileggi

{"title":"Analog and RF circuit macromodels for system-level analysis","authors":"Xin Li, Peng Li, Yang Xu, L. Pileggi","doi":"10.1109/DAC.2003.1219048","DOIUrl":"https://doi.org/10.1109/DAC.2003.1219048","url":null,"abstract":"Design and validation of mixed-signal integrated systems require system-level model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF component macromodels, but their complexity can sometimes limit their utility for time-varying systems and large circuits with complex device models or numerous parasitics. In this paper we propose simple and efficient analog and RF circuit macromodels that provide accurate model abstractions for large, complex time-varying circuits over frequency bands of interest. By starting with the system-level block diagram model structures and focusing on the narrow RF bands, the proposed macromodels can efficiently capture the nonlinear behavior as well as the impact of RLC coupling parasitics via compact reduced-order model forms. While the macromodel can trade accuracy for simplicity in terms of the number of frequency expansion points, we find that expansion about one frequency point provides the accuracy required for system-level analysis of most RF and narrow-band analog components. The macromodel form corresponds to block diagram structures that are easily incorporated into our system-level simulation tool based on Simulink.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124582923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Parameter variations and impact on circuits and microarchitecture 参数变化及其对电路和微结构的影响

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775920

S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De

引用次数: 1526

Optimizations for a simulator construction system supporting reusable components 支持可重用组件的模拟器构建系统的优化

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.776065

D. Penry, David I. August

引用次数: 37

4G terminals: how are we going to design them? 4G终端:我们将如何设计?

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775855

J. Craninckx, S. Donnay

引用次数: 26

A fully programmable memory management system optimizing queue handling at multi gigabit rates 一个完全可编程的内存管理系统优化队列处理在多千兆速率

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI: 10.1145/775832.775849

Georgios Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos

{"title":"A fully programmable memory management system optimizing queue handling at multi gigabit rates","authors":"Georgios Kornaros, I. Papaefstathiou, A. Nikologiannis, N. Zervos","doi":"10.1145/775832.775849","DOIUrl":"https://doi.org/10.1145/775832.775849","url":null,"abstract":"Two of the main bottlenecks when designing a network embedded system are very often the memory bandwidth and its capacity. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced quality of service (QoS), per-flow queuing is desirable. In this paper we describe the architecture of a memory manager that can provide up to 10Gbs of aggregate throughput while handling 512K queues. The presented system supports a complete instruction set and thus we believe it can be used as a hardware component in any suitable embedded system, particularly network SoCs that implement per flow queuing. When designing this scheme several optimization techniques have been evaluated and the most cost and performance effective ones used. These techniques minimize both the memory bandwidth and the memory capacity needed, which is considered a main advantage of the proposed scheme. The proposed architecture uses a simple DRAM for data storage and a typical SRAM for keeping data structures-pointers, therefore minimizing the system's cost. The device has been fabricated within a novel programmable network processor designed for efficient protocol processing in high speed networking applications. It consists of 155K gates and occupies 5.23 mm/sup 2/ in UMC 0.18 /spl mu/m CMOS.","PeriodicalId":167477,"journal":{"name":"Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116482471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24