Verilog HDL，由PLI提供支持:在所有抽象级别上描述和建模异步电路的合适框架

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI:10.1145/775832.775917

Arash Saifhashemi, H. Pedram

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引用次数: 50

摘要

在本文中，我们展示了如何使用Verilog HDL和PLI(编程语言接口)通过实现CSP(通信顺序进程)语言结构来在行为层面上建模异步电路。在Verilog HDL中，通道和通信动作被建模为抽象动作。

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Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.

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Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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