2011 IEEE Computer Society Annual Symposium on VLSI最新文献

Thermal Analysis of Advanced 3D Stacked Systems 先进3D堆叠系统的热分析

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.36

Kameswar Rao Vaddina, A. Rahmani, Khalid Latif, P. Liljeberg, J. Plosila

引用次数: 5

Synthesis of Analog IC Building Blocks 模拟集成电路构建模块的合成

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.37

A. Agarwal, C. Shekhar

{"title":"Synthesis of Analog IC Building Blocks","authors":"A. Agarwal, C. Shekhar","doi":"10.1109/ISVLSI.2011.37","DOIUrl":"https://doi.org/10.1109/ISVLSI.2011.37","url":null,"abstract":"A new methodology based on the concept of performance based figure of merit, has been proposed for synthesizing optimal performance differential input-stage amplifiers and second stage amplifier under the constraints of area. This concept has been validated with examples both at low and medium frequencies. The proposed figures of merit proposed for different structures and in different frequency domains peak at certain values of relative area allocation to the input transistors in the range of 62 % to 92 % of the available area. The peak achievable value of the figure of merit is a function of both area and power. It is observed that the performance parameters, i.e. differential dc voltage gain, unity-gain bandwidth and input-referred noise achieved at peak figure of merit are very close to their best individually achievable values. Using this concept, a CAD tool has been developed in C/C++, for the synthesis of differential amplifiers and tested for 2400 design-syntheses with varying dc power, differential dc voltage gain, unity-gain bandwidth and input-referred noise. The synthesized circuits are mainly governed by power and noise. At a constant power, area required increases exponentially with the requirement of reduced input-referred noise. Area requirement can also be reduced at the cost of increased power consumption for the same input-referred noise. Hence, a clear Area -- Power tradeoff is seen in the synthesized designs.","PeriodicalId":167365,"journal":{"name":"2011 IEEE Computer Society Annual Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122383520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCs 基于noc的mpsoc上基于预处理的应用运行时映射

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.43

S. Kaushik, Ashutosh Kumar Singh, T. Srikanthan

引用次数: 8

Next Generation Smart Home Systems Using Hardware Acceleration Techniques 下一代智能家居系统使用硬件加速技术

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.83

David Fuschelberger, Ioannis Pyrounakis, T. Dagiuklas, N. Voros, Carlos Ribeiro

引用次数: 1

Architectures for Simultaneous Coding and Encryption Using Chaotic Maps 使用混沌映射的同时编码和加密体系结构

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.14

A. Pande, Joseph Zambreno, P. Mohapatra

引用次数: 4

Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET 栅极- s /D重叠、不对称和独立栅极特性对减小纳米级DGMOSFET短沟道效应的影响

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.22

R. Vaddi, S. Dasgupta, R. P. Agarwal

引用次数: 4

A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion 一种改善时钟延迟和路由拥塞的混合射频/金属时钟路由算法

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.87

Zohre Mohammadi-Arfa, A. Jahanian

引用次数: 2

Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC 用于并行流水线ADC的低功耗、高速互补输入折叠调节级联码OTA设计

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.9

M. K. Hati, T. K. Bhattacharyya

{"title":"Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC","authors":"M. K. Hati, T. K. Bhattacharyya","doi":"10.1109/ISVLSI.2011.9","DOIUrl":"https://doi.org/10.1109/ISVLSI.2011.9","url":null,"abstract":"This paper presents a low-power, high speed complementary input folded regulated cascode operational transconductance amplifier (OTA) designed for the 10bit, 150MSPS parallel pipeline ADC. The OTA plays an important role in the ADC, because of its conversion rate and power consumption are limited by the performance of the OTA. The designed ADC in this paper employs parallel pipeline architecture based on double sampling sampled hold (DSSH) technique, and shares the OTA between two channels of the ADC. The folded cascode OTA consists of fully differential and regulated cascode gain boosting technique. Besides, a Common Mode Feed Back (CMFB) circuit was introduced and some methods are concerned to improve the performance. Then, by proper optimization of the layout design, OTA's mismatch was reduced up-to a great extent. With 1.8V power supply, using the CMOS9T5V 180nm process technology, the simulation shows that the open-loop gain of the OTA is 90.39 dB, the phase margin (PM) is 63.85° with the unity gain bandwidth (UGB) of 700.7 MHz. The power consumption of this OTA is only 3.24 mW, which significantly reduces the whole power consumption of the parallel pipeline ADC.","PeriodicalId":167365,"journal":{"name":"2011 IEEE Computer Society Annual Symposium on VLSI","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132157047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC 软容错MPSoC的一种软硬件协同方法

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.48

Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, M. Nikdast, Zhehui Wang

{"title":"A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC","authors":"Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, M. Nikdast, Zhehui Wang","doi":"10.1109/ISVLSI.2011.48","DOIUrl":"https://doi.org/10.1109/ISVLSI.2011.48","url":null,"abstract":"Multiprocessor systems-on-chip (MPSoCs) are attractive platforms for embedded applications with growing complexity, because integrating a system or a complex subsystem on a single chip provides better performance and energy efficiency and lower cost per function. As feature sizes and power supply voltages continually decrease, MPSoCs are becoming more susceptible to soft errors. However, traditional soft-error tolerant methods introduce large area, power and performance overheads to MPSoCs. This paper presents a low-overhead hardware-software collaborated method, called SENoC, to dynamically mitigate soft errors on MPSoCs using an on-chip sensor network. We developed a low-cost on-chip sensor network to collaboratively monitor and detect soft errors, and implemented software-based mechanisms to guarantee correct task executions. To maximize the performance of soft-error tolerant MPSoCs, a hybrid scheduling scheme is proposed to effectively manage applications and resources under uncertainties. We studied the new method on MPSoCs with different scales and tested it using typical embedded applications under different cosmic ray flux conditions. Experimental results show that comparing to traditional methods SENoC requires substantially lower protection overheads to achieve the same level of soft-error tolerance. For instance, soft-error tolerant MPSoCs using SENoC archive on average 114.1% better performance than a latest traditional method, and SENoC only introduces 0.42% area overhead to a 256-core MPSoCs.","PeriodicalId":167365,"journal":{"name":"2011 IEEE Computer Society Annual Symposium on VLSI","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117176681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs 通过多路tsv缓解3D ic中的分区、路由和良率问题

2011 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2011-07-04 DOI: 10.1109/ISVLSI.2011.27

Michael Buttrick, S. Kundu

{"title":"Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs","authors":"Michael Buttrick, S. Kundu","doi":"10.1109/ISVLSI.2011.27","DOIUrl":"https://doi.org/10.1109/ISVLSI.2011.27","url":null,"abstract":"Vertical stacking of integrated circuits has figured prominently in the International Technology Roadmap of Semiconductors. 3D ICs reduce global interconnect lengths, allow mixed technologies including DRAM and Flash, enables silicon reuse, and delivers power, performance and cost benefits. However, die-stacking requires inter-die interconnects known as through silicon vias (TSVs) that tend to be limited in number due to manufacturing and reliability concerns. This limitation constrains partitioning at the system level, affects routing area used by TSVs, and diminishes the benefit of vertical stacking. Here we present a means to increase the effective number of inter-die connections in 3D integrated circuits to mitigate such limitations. In the proposed solution, two signals originating in one die are multiplexed by the system clock and recovered by a combination of positive and negative edge-triggered flip-flops on the destination die. Also proposed is an extension where the signals need not originate on the same die. This method of multiplexing TSVs allows for the doubling of inter-die connections with very little area overhead or intrinsic performance overhead. Results show that this simple scheme unlocks the full potential of 3D in many designs which would not have been possible otherwise.","PeriodicalId":167365,"journal":{"name":"2011 IEEE Computer Society Annual Symposium on VLSI","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128293380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1