A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion

Abstract

Global clock network has been a major limitation on delay, power and routing resources in modern VLSI circuits. Recently, some methods are proposed to use RF instruments for on-chip clock routing in large chips but they suffer from large power and area overhead. In this paper, a hybrid RF/metal clock networking is presented which combines the benefits of RF/wireless Interconnect and Cu/wired interconnects. Our experiments show that clock network delay and clock tree congestion are improved by 64\% and 40% on average in a cost of 1.9% area overhead and less than 10% power consumption overhead for large circuits. Moreover, power consumption overhead will be reduced for larger circuits and smaller featured sized technologies.