2014 IEEE Workshop on Signal Processing Systems (SiPS)最新文献

High-performance sparse fast Fourier transforms 高性能稀疏快速傅里叶变换

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986055

J. Schumacher, Markus Püschel

引用次数: 28

Energy-efficient vision on the PULP platform for ultra-low power parallel computing 超低功耗并行计算的PULP平台节能愿景

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986099

Francesco Conti, D. Rossi, A. Pullini, Igor Loi, L. Benini

引用次数: 29

Acceleration of clustering-based superpixel algorithms with low memory costs 基于聚类的低内存开销超像素算法的加速

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986095

Tse-Wei Chen, Noriyasu Hashiguchi, M. Ariizumi, Kinya Osa, Daisuke Nakashima, Yasuo Fukuda, Shiori Wakino, Shinji Shiraga, Masami Kato

{"title":"Acceleration of clustering-based superpixel algorithms with low memory costs","authors":"Tse-Wei Chen, Noriyasu Hashiguchi, M. Ariizumi, Kinya Osa, Daisuke Nakashima, Yasuo Fukuda, Shiori Wakino, Shinji Shiraga, Masami Kato","doi":"10.1109/SiPS.2014.6986095","DOIUrl":"https://doi.org/10.1109/SiPS.2014.6986095","url":null,"abstract":"As a pre-processing step of image segmentation, superpixel algorithms are used to produce small, uniform and compact regions, which can be used for region-based image coding, region-based image processing, and object recognition. In order to meet the requirements of real-time applications for embedded computing, it is necessary to reduce the computational costs of superpixel algorithms and increase the processing speed. In this paper, a series of acceleration schemes for superpixels algorithm is proposed. The features and contributions of this work are stated as follows. Firstly, the spatial distances and the color distances are calculated individually, so that the redundant distance computations can be saved. Secondly, by searching the nearest cluster centroids with centroid priority, the nearest clusters can be found at an early stage. Thirdly, the early-termination mechanism can be applied to the search process to speed up the algorithm without decreasing the quality of image segmentation. Fourthly, the storage for label images and distance images is not required since the operations of nearest centroids are processed in the inner loop of the algorithm. The experiments show that the proposed method achieves the same level of performance as the related work with only 75% of distance computations and 33% of memory costs.","PeriodicalId":167156,"journal":{"name":"2014 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128595580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Composite data fusion algorithm for miniature vehicles building navigation base in formation flying 编队飞行中微型飞行器建立导航基地的复合数据融合算法

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986068

Runle Du, Jiaqi Liu, Zhifeng Li, Zhenhong Niu, Zhiye Jiang, Yadong Yang

引用次数: 0

Accelerating integer-based fully homomorphic encryption using Comba multiplication 使用Comba乘法加速基于整数的全同态加密

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986063

C. Moore, Máire O’Neill, Neil Hanley, E. O'Sullivan

{"title":"Accelerating integer-based fully homomorphic encryption using Comba multiplication","authors":"C. Moore, Máire O’Neill, Neil Hanley, E. O'Sullivan","doi":"10.1109/SiPS.2014.6986063","DOIUrl":"https://doi.org/10.1109/SiPS.2014.6986063","url":null,"abstract":"Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.","PeriodicalId":167156,"journal":{"name":"2014 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114953432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

On modified EMD: Selective extrema analysis 改进EMD:选择性极值分析

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986070

Asma Qureshi, Maite Brandt-Pearce

{"title":"On modified EMD: Selective extrema analysis","authors":"Asma Qureshi, Maite Brandt-Pearce","doi":"10.1109/SiPS.2014.6986070","DOIUrl":"https://doi.org/10.1109/SiPS.2014.6986070","url":null,"abstract":"The Empirical Mode Decomposition (EMD) algorithm was introduced as the first step of the Hilbert-Huang Transform, proposed by Huang et al. (1998). EMD decomposes a signal into so-called Intrinsic Mode Functions (IMFs) in a systematic way. Since then, various versions of EMD have been developed, addressing weaknesses of the original EMD procedure and aiming to optimize the original algorithm in a number of ways. This paper The Empirical Mode Decomposition (EMD) algorithm was introduced as the first step of the Hilbert-Huang Transform, proposed by Huang et al. (1998). EMD decomposes a signal into so-called Intrinsic Mode Functions (IMFs) in a systematic way. Since then, various versions of EMD have been developed, addressing weaknesses of the original EMD procedure and aiming to optimize the original algorithm in a number of ways. This paper proposes to use selective extrema analysis while generating IMFs with two goals. One is to reduce/control the number of IMFs a signal is decomposed into with a small decomposition error, and second is to make EMD insensitive to small variations in the analyzed signal. The proposed algorithm is applied to a gait signal and shown to consistently yield two IMFs, even in the presence of small disturbances.proposes to use selective extrema analysis while generating IMFs with two goals. One is to reduce/control the number of IMFs a signal is decomposed into with a small decomposition error, and second is to make EMD insensitive to small variations in the analyzed signal. The proposed algorithm is applied to a gait signal and shown to consistently yield two IMFs, even in the presence of small disturbances.","PeriodicalId":167156,"journal":{"name":"2014 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132301727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A search-less DEC BCH decoder for low-complexity fault-tolerant systems 用于低复杂度容错系统的无搜索DEC BCH解码器

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986060

Injae Yoo, I. Park

引用次数: 7

Effect of computation offload on performance and energy consumption of mobile face recognition 计算负载对移动人脸识别性能和能耗的影响

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986056

Nanoka Sumi, A. Baba, V. Moshnyaga

引用次数: 5

Programmable in-loop deblock filter processor for video decoders 用于视频解码器的可编程环内块滤波器处理器

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986071

Janne Janhunen, P. Jääskeläinen, J. Hannuksela, Tero Rintaluoma, Aki Kuusela

{"title":"Programmable in-loop deblock filter processor for video decoders","authors":"Janne Janhunen, P. Jääskeläinen, J. Hannuksela, Tero Rintaluoma, Aki Kuusela","doi":"10.1109/SiPS.2014.6986071","DOIUrl":"https://doi.org/10.1109/SiPS.2014.6986071","url":null,"abstract":"The short time to market cycle and the target to reduce design and verification costs are driving forces to design programmable implementations of the video processing algorithms. We present two processor architectures the first one representing an application-specific instruction set processor (ASIP) design, whereas the second architecture represents a domain-specific instruction-set processor (DSIP) architecture with more general purpose instruction-set. In this work, we present results for H264 and VP8 in-loop deblocking algorithms. The processors are based on the transport triggered architecture which provides scalable instruction-level parallelism and, thanks to its simple structure, lend itself to cost effective designs. Both of the designs are programmed with C language with a minimal additional parallelism markup. The designs fulfill realtime requirements for filtering macroblocks in high-definition video. The first architecture, based on special function units, filters a high-definition stream (1920 × 1080) at 75 fps, whereas the second architecture, which provides a better programmability, filters the stream at 53 fps. The processors run on 200 MHz clock frequency and the areas vary from 146k to 373k gate equivalents depending on the processor architecture.","PeriodicalId":167156,"journal":{"name":"2014 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134403777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories 基于全并行集群联想记忆的多域上下文驱动搜索引擎的算法和体系结构

2014 IEEE Workshop on Signal Processing Systems (SiPS) Pub Date : 2014-12-18 DOI: 10.1109/SiPS.2014.6986075

Hooman Jarollahi, N. Onizawa, Vincent Gripon, T. Hanyu, W. Gross

引用次数: 5