{"title":"Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI","authors":"T. Sugawara, D. Suzuki, T. Katashita","doi":"10.1109/FDTC.2012.17","DOIUrl":"https://doi.org/10.1109/FDTC.2012.17","url":null,"abstract":"Circuit simulation method for Fault Sensitivity Analysis (FSA) is proposed. The simulation can be used both for (i) security evaluation before fabrication and (ii) investigation of leak mechanism. The proposed method extracts fault sensitivity data from post place-and-route logic simulation results, thus it can easily be integrated with conventional LSI design flow. As a proof of concept, the proposed method is applied to netlist of an AES implementation on 130-nm SASEBO LSI. In the experiment, key recovery attack is successfully recreated using simulated data of a standard implementation (AES_Comp). In addition, to bridge a gap between the simulation and real measurement, we model the effect of induced timing jitter (measurement noise) on the resulting correlation.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Techniques for EM Fault Injection: Equipments and Experimental Results","authors":"P. Maurine","doi":"10.1109/FDTC.2012.21","DOIUrl":"https://doi.org/10.1109/FDTC.2012.21","url":null,"abstract":"This paper will show that EM backside injection (case of flip chip bga packages) has little or no interest. Indeed, a new fault injection technique, called Forward Body Biaising Injection (FBBI), must be preferred to EM injection to produce transient faults, especially when LASER shots are detected by the target. The equipment required to apply a FBBI is low cost and really similar to the one used to produce an EM pulse. It is shown in 3. The main difference is the replacement of the coil producing the magnetic field by a thin tungsten rod in order to directly establish an electrical contact with the substrate. With such a direct contact (instead of a magnetic coupling), the fault can be produced with a low amplitude pulse generator. Additionally, the spatial resolution is expected to be better than with an EM pulse. The two electrical behaviors underlying this simple technique will be described before giving some experimental results obtained on a CRT based RSA, running on a secure device featuring a modular arithmetic co-processor.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123707256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Järvinen, Céline Blondeau, D. Page, Michael Tunstall
{"title":"Harnessing Biased Faults in Attacks on ECC-Based Signature Schemes","authors":"K. Järvinen, Céline Blondeau, D. Page, Michael Tunstall","doi":"10.1109/FDTC.2012.13","DOIUrl":"https://doi.org/10.1109/FDTC.2012.13","url":null,"abstract":"This paper presents an extension of the byte-fault attack on signature schemes presented by Giraud et al. Our work extends their attack in a number of ways, but the main focus is an alternative fault model motivated by existing fault injection results. Instead of assuming faults are uniformly distributed (i.e., a given bit is flipped with probability 1/2), we consider the case where faults are biased (i.e., the probability differs from 1/2). Our results show that injecting biased faults allows an attacker to reveal security-critical data with significantly fewer faults and/or a significantly faster search through the remaining candidates.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132681879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sébastien Briais, Jean-Michel Cioranesco, J. Danger, S. Guilley, D. Naccache, Thibault Porteboeuf
{"title":"Random Active Shield","authors":"Sébastien Briais, Jean-Michel Cioranesco, J. Danger, S. Guilley, D. Naccache, Thibault Porteboeuf","doi":"10.1109/FDTC.2012.11","DOIUrl":"https://doi.org/10.1109/FDTC.2012.11","url":null,"abstract":"Recently, some active shielding techniques have been broken (e.g. by FlyLogic). The caveat is that their geometry is easy to guess, and thus they can be bypassed with an affordable price. This paper has two contributions. First of all, it provides a definition of the objectives of shielding, which is seldom found in publicly available sources. Notably, we precise the expected functionality, but also the constraints it must meet to be both manufacturable and secure. Second, we propose an innovative solution based on random shielding. The goal of this shielding is to make the geometry of the shield difficult to recognize, thereby making the \"identification\" phase of the attack harder than in previous schemes. Also, a proof of the shielding existence for two layers of metal is provided, which guarantees that the generation of the layout will succeed. Finally, we provide real tests of the shield generation algorithm, that show it is computationally tractable even for large areas to protect.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116148758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the Need of Randomness in Fault Attack Countermeasures - Application to AES","authors":"Victor Lomné, Thomas Roche, Adrian Thillard","doi":"10.1109/FDTC.2012.19","DOIUrl":"https://doi.org/10.1109/FDTC.2012.19","url":null,"abstract":"Recent works show that a combination of perturbation and observation attacks on symmetric ciphers thwarts state-of-the-art countermeasures. In this paper, we first propose a new way - to our knowledge - to classify fault attacks against block ciphers, allowing us to exhibit their capacity to be combined with observation attacks. We then present a set of common protections against side-channel and fault attacks, namely higher-order masking schemes, detection and infection countermeasures, and how they can be combined. We show that the combination of a higher-order masking scheme and a detection countermeasure can actually be defeated by a slight variant of the combined attack of Roche et al., even if one applies their patch. Furthermore, we also demonstrate that none of the published infection countermeasures is robust against fault attacks. Finally, using randomness, we propose a set of enhanced countermeasures that thwart considered threats.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ronan Lashermes, Guillaume Reymond, J. Dutertre, J. Fournier, B. Robisson, A. Tria
{"title":"A DFA on AES Based on the Entropy of Error Distributions","authors":"Ronan Lashermes, Guillaume Reymond, J. Dutertre, J. Fournier, B. Robisson, A. Tria","doi":"10.1109/FDTC.2012.18","DOIUrl":"https://doi.org/10.1109/FDTC.2012.18","url":null,"abstract":"Differential fault analysis (DFA) techniques have been widely studied during the past decade. To our best knowledge, most DFA techniques on the Advanced Encryption Standard (AES) either impose strong constraints on the fault injection process or require numerous faults in order to recover the secret key. This article presents a simple methodology based on information theory which allows to adapt the number of required faults for the analysis to the fault injection process. With this technique, the constraints on the fault model to recover the last round key are considerably lowered. Additionally, entropy is proposed as a tool to apprehend the most complex fault models in DFA. A practical realization and simulations are presented to illustrate our methodology.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"It's Not My Fault - On Fault Attacks on Symmetric Cryptography","authors":"B. Preneel","doi":"10.1109/FDTC.2012.20","DOIUrl":"https://doi.org/10.1109/FDTC.2012.20","url":null,"abstract":"Symmetric cryptographic algorithms include stream ciphers, block ciphers, MAC algorithms, and hash functions. This paper discusses the generations of these algorithms and how these generations are affected by fault attacks. It also offers a perspective on approaches that could offer increased resistance against fault attacks and other implementation attacks.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127338220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Combined Fault and Side-Channel Attacks on the AES Key Schedule","authors":"François Dassance, Alexandre Venelli","doi":"10.1109/FDTC.2012.10","DOIUrl":"https://doi.org/10.1109/FDTC.2012.10","url":null,"abstract":"We present combined attacks on the AES key schedule based on the work of Roche et al. [1]. The main drawbacks of the original attack are: the need for high repeatability of the fault, a very particular fault model and a very high complexity of the key recovery algorithm. We consider more practical fault models, we obtain improved key recovery algorithms and we present more attack paths for combined attacks on AES. We propose to inject faults on the different operations of the key schedule instead of the key state of round 9 or the corresponding data state. We also consider fault injections in AES constants such as the RCon or the affine transformation of the SubWord. By corrupting these constants, the attacker can easily deduce the value of the error. The key recovery complexity can then be greatly improved. Notably, we can obtain a complexity identical to a classical differential side-channel attack. Our attacks defeat most AES implementations secure against both high-order side-channel attacks and fault attacks.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128249792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electromagnetic Transient Faults Injection on a Hardware and a Software Implementations of AES","authors":"Amine Dehbaoui, J. Dutertre, B. Robisson, A. Tria","doi":"10.1109/FDTC.2012.15","DOIUrl":"https://doi.org/10.1109/FDTC.2012.15","url":null,"abstract":"This paper considers the use of electromagnetic pulses (EMP) to inject transient faults into the calculations of a hardware and a software AES. A pulse generator and a 500 um-diameter magnetic coil were used to inject the localized EMP disturbances without any physical contact with the target. EMP injections were performed against a software AES running on a CPU, and a hardware AES (with and without countermeasure) embedded in a FPGA. The purpose of this work was twofold: (a) reporting actual faults injection induced by EMPs in our targets and describing their main properties, (b) explaining the coupling mechanism between the antenna used to produce the EMP and the targeted circuit, which causes the faults. The obtained results revealed a localized effect of the EMP since the injected faults were found dependent on the spatial position of the antenna on top of the circuit's surface. The assumption that EMP faults are related to the violation of the target's timing constraints was also studied and ascertained thanks to the use of a countermeasure based on monitoring such timing violations.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130202574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Endo, Yang Li, N. Homma, K. Sakiyama, K. Ohta, T. Aoki
{"title":"An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks","authors":"S. Endo, Yang Li, N. Homma, K. Sakiyama, K. Ohta, T. Aoki","doi":"10.1109/FDTC.2012.12","DOIUrl":"https://doi.org/10.1109/FDTC.2012.12","url":null,"abstract":"In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis (DFA) such as redundancy calculation, Masked AND-OR and Wave Dynamic Differential Logic (WDDL). The proposed countermeasure can detect both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept which removes the dependency between fault sensitivities and secret data. Post-manufacture configuration of the delay blocks allows minimization of the overhead in operating frequency which comes from manufacture variability. In this paper, we present an implementation of the proposed countermeasure, and describe its configuration method. We also investigate the hardware overhead of the proposed countermeasure implemented in ASIC for an AES module and demonstrate its validity through an experiment using a prototype FPGA implementation.","PeriodicalId":165647,"journal":{"name":"2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127456715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}