发布求助
文献互助 智能选刊 最新文献

2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

筛选
英文 中文
A 30-MHz-to-3-GHz CMOS array receiver with frequency and spatial interference filtering for adaptive antenna systems 一种用于自适应天线系统的带有频率和空间干扰滤波的30mhz - 3ghz CMOS阵列接收机
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508318
Naoki Oshima, M. Kitsunezuka, K. Tsukamoto, K. Kunihiro
{"title":"A 30-MHz-to-3-GHz CMOS array receiver with frequency and spatial interference filtering for adaptive antenna systems","authors":"Naoki Oshima, M. Kitsunezuka, K. Tsukamoto, K. Kunihiro","doi":"10.1109/RFIC.2016.7508318","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508318","url":null,"abstract":"A 30-MHz-to-3-GHz wideband CMOS phased array receiver with interference suppression capability in frequency and spatial domains is presented. A frequency filtering function is provided by a 16-phase, two-stage harmonic rejection mixer which also works as a 5-bit phase shifter in multi-chip phased array systems. Equipped with 6-bit amplitude control in addition to the phase, the array receiver enables analog null steering that can reduce a spatial interferer coming from a specific direction. The developed IC achieves more than 55-dB suppression of harmonic interference in the wide range from 30 MHz to 3 GHz. The multiple ICs configure a four-element adaptive array system for the measurement of space propagation. It is confirmed that the null steering function reduces spatial interference by 20 dB and improves an EVM from -12.7 dB to -26.3 dB even when a strong interferer exists.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115871177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 3-stage recursive Weaver image-reject receiver 三级递归韦弗图像拒绝接收器
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508259
R. Srinivasan, Wei-Gi Ho, R. Gharpurey
{"title":"A 3-stage recursive Weaver image-reject receiver","authors":"R. Srinivasan, Wei-Gi Ho, R. Gharpurey","doi":"10.1109/RFIC.2016.7508259","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508259","url":null,"abstract":"A low-power Weaver image-reject receiver based on 3rd-order signal recursion is demonstrated. The design employs two downconverters and seeks to enhance the dynamic range and gain-bandwidth product per unit power dissipation metric by adopting recursive gain reuse at multiple frequencies. Utilizing an LO at frequency fLO, the downconverter recursively amplifies an RF signal at fRF at 3 distinct frequencies, namely fRF, fRF - fLO and fRF - 2fLO, while using the same DC bias current. Further, the receiver uses the same quadrature mixers to perform the two frequency translations. The design is implemented in a 130 nm CMOS process. Over a current range from 650 μA to 2 mA, employing a supply voltage of 1.2V, the design achieves a corresponding conversion gain in the range from 57.2-82.7 dB, flicker noise corner <; 20 kHz, and a SSBNF of 13.6-6.8 dB for fRF = 404/434 MHz, in each downconverter. The architecture is suitable for application in a low-IF MICS/ISM band receiver, and low-power sensor applications.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131934412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fully integrated 320 pJ/b OOK super-regenerative receiver with −87 dBm sensitivity and self-calibration 完全集成的320 pJ/b OOK超再生接收机，灵敏度为- 87 dBm，具有自校准功能
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508291
V. Rezaei, S. Shellhammer, Mohamed Elkholy, K. Entesari
{"title":"A fully integrated 320 pJ/b OOK super-regenerative receiver with −87 dBm sensitivity and self-calibration","authors":"V. Rezaei, S. Shellhammer, Mohamed Elkholy, K. Entesari","doi":"10.1109/RFIC.2016.7508291","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508291","url":null,"abstract":"This paper presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. It exploits a SAR architecture to calibrate the internally generated quench signal. Employing an on-chip inductor and a single to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 μW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate, while the best sensitivity is -87 dBm at 1 Mb/s data rate.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120867701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A low power high performance PLL with temperature compensated VCO in 65nm CMOS 一种低功耗高性能锁相环，带65nm CMOS温度补偿压控振荡器
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508243
V. Ravinuthula, S. Finocchiaro
{"title":"A low power high performance PLL with temperature compensated VCO in 65nm CMOS","authors":"V. Ravinuthula, S. Finocchiaro","doi":"10.1109/RFIC.2016.7508243","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508243","url":null,"abstract":"This paper presents a fully integrated, low power, low noise Phase-Locked Loop (PLL) implementing a temperature compensated class-C dual-core Voltage Controlled Oscillator (VCO) achieving state of the art phase noise performance. The PLL exhibits low integrated noise enabling the integration of low jitter clocks for high performance data converters supporting GSM requirements for Wireless Infrastructure applications. Implemented in 65 nm CMOS process, the 8 GHz VCO achieves Phase Noise of -140 dBc/Hz at 1 MHz offset measured at 2 GHz output. The PLL exhibits -60 dBc rms noise integrated from 10 kHz to 20 MHz, while maintaining lock for the ambient temperature range -40°C to 105°C, and dissipating ≈ 140 mW.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126679825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 2.8–4.3GHz wideband fractional-N sub-sampling synthesizer with −112.5dBc/Hz in-band phase noise 2.8-4.3GHz宽带分数n次采样合成器，带内相位噪声为- 112.5dBc/Hz
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508267
M. M. Bajestan, H. Attah, K. Entesari
{"title":"A 2.8–4.3GHz wideband fractional-N sub-sampling synthesizer with −112.5dBc/Hz in-band phase noise","authors":"M. M. Bajestan, H. Attah, K. Entesari","doi":"10.1109/RFIC.2016.7508267","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508267","url":null,"abstract":"A 2.8-4.3GHz low noise fractional-N subsampling frequency synthesizer in 40nm CMOS technology is presented in this paper. The reference sampling clock is modulated by a 10-bit edge modulator to achieve fractional phase lock. A novel fast two-step background calibration is used to correct gain errors in the edge modulator, reducing fractional spurs. For a 3.75GHz carrier, the synthesizer achieves 376fs rms jitter with a worst case fractional spur of -48.3dBc. The in-band phase noise at 200kHz offset is -112.5dBc/Hz. The system consumes a total power of 9.18mW from a 1.1V supply and occupies an area of 0.41mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121703456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An E-band, scalable 2×2 phased-array transceiver using high isolation injection locked oscillators in 90nm SiGe BiCMOS e波段，可扩展2×2相控阵收发器使用高隔离注入锁定振荡器在90nm SiGe BiCMOS
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI: 10.1109/RFIC.2016.7508280
Najme Ebrahimi, M. Bagheri, Po-Yi Wu, J. Buckwalter
{"title":"An E-band, scalable 2×2 phased-array transceiver using high isolation injection locked oscillators in 90nm SiGe BiCMOS","authors":"Najme Ebrahimi, M. Bagheri, Po-Yi Wu, J. Buckwalter","doi":"10.1109/RFIC.2016.7508280","DOIUrl":"https://doi.org/10.1109/RFIC.2016.7508280","url":null,"abstract":"This paper presents the first E-band phased array transceiver that uses injection locked oscillators (ILOs) for beamforming. We propose a current injection distribution network with wide locking range and high isolation. A 2×2 bidirectional transceiver is demonstrated to operate from 71-86 GHz and measurements verify that each oscillator can be controlled independently with phase shift over ±300 degrees with <; 5° phase error and under 0.9 dB amplitude variation. Each channel has a 9.5-dB noise figure in RX mode and a 10-dBm output power in TX mode. The phase noise of the locked oscillator exhibits less than 2.5 dB variation across the phase steering range. The 90-nm SiGe BiCMOS chip consumes 386.4 mW in TX mode and 286 mW in RX mode per channel.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133210982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信