{"title":"Building a Symbolic Model Checker from Formal Language Description","authors":"Edmundo López Bóbeda, Maximilien Colange, Didier Buchs","doi":"10.1109/ACSD.2015.10","DOIUrl":"https://doi.org/10.1109/ACSD.2015.10","url":null,"abstract":"The main limit towards practical model-checking is the combinatorial explosion of the number of states. Among numerous solutions proposed to tackle this problem, Decision Diagrams (DDs) have been proved efficient. They are however low-level data structures: translating a high-level model to them can be cumbersome. Indeed, little work towards their better usability has been undertaken. We propose an abstract mechanism for the manipulation of DDs, where system transitions are described in terms of rewrite rules. We describe how basic rewrite rules can be assembled through strategies, to describe complex transition relations (e.g. involving various levels of synchronization among parallel components). The strategies and rewrite rules offer a higher-level interface, where the nature of underlying DD is hidden, close to high-level languages used to model concurrent systems. We also describe specific strategies that we use to automatically translate high-level modeling languages (namely Petri Nets and imperative languages) to rewrite strategies, ultimately translated in terms of operations on DDs.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"63 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114115655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Framework for Composition, Verification and Real-Time Performance of Multimedia Interactive Scenarios","authors":"Jaime Arias, M. Desainte-Catherine, C. Rueda","doi":"10.1109/ACSD.2015.8","DOIUrl":"https://doi.org/10.1109/ACSD.2015.8","url":null,"abstract":"Interactive Scores (IS) is a formalism for composing and performing interactive multimedia scenarios. In IS, the composer defines temporal relations (TRs) between temporal objects (TOs) in order to specify the temporal organization of the scenario. During execution, the performer may trigger interaction points to modify the star/stop times of TOs, while the system guarantees that all the TRs are satisfied. IS is implemented in the tool I-SCORE and its semantics is formally defined as a Hierarchical Time Stream Petri Net (HTSPN). However, this model is not able to represent branching behaviors that are necessary to properly deal with applications such as video games and museum installations. Moreover, HTSPN does not provide tools for the automatic verification of critical properties of scenarios. In this work we define a semantics for IS based on Timed Automata (TA) and we show that such model yields to a complete framework to compose, verify and execute interactive scenarios. More precisely, we show that: 1) our model is able to deal with conditional statements in IS; 2) efficient verification techniques can be now used to reason about the written scenarios; and 3) our model allows for a directly implementation on a reconfigurable device, thus guaranteeing a real-time performance.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"155 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128666276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Heuristic Algorithm for Deriving Compact Models of Processor Instruction Sets","authors":"Alessandro de Gennaro, P. Stankaitis, A. Mokhov","doi":"10.1109/ACSD.2015.17","DOIUrl":"https://doi.org/10.1109/ACSD.2015.17","url":null,"abstract":"Finding a compact formal representation of a processor instruction set is important for easier comprehension by the designer, as well as for synthesis of an efficient hardware implementation of the processor's microcontroller. We present a new heuristic algorithm for deriving compact models of processor instruction sets. The algorithm is based on finding similarities between pairs of instructions and assigning similar opcodes (using a Hamming distance metric) to similar instructions (using a newly introduced instruction similarity metric). We demonstrate that this heuristic produces results with an average overhead, in terms of area, of 7.8% in comparison to the global optimum on the benchmarks we studied (subsets of instructions of ARM Cortex M0+, Texas Instruments MSP430 and Intel 8051 processors).The algorithm is implemented as an open-source plugin for the Workcraft framework and is validated on a case study of a subset of 61 (out of 68) instructions of ARM Cortex M0+ processor. We compare the presented algorithm against a number of other available implementations.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133135730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Rafiev, Fei Xia, A. Iliasov, Rem Gensh, Ali Aalsaud, A. Romanovsky, A. Yakovlev
{"title":"Order Graphs and Cross-Layer Parametric Significance-Driven Modelling","authors":"A. Rafiev, Fei Xia, A. Iliasov, Rem Gensh, Ali Aalsaud, A. Romanovsky, A. Yakovlev","doi":"10.1109/ACSD.2015.16","DOIUrl":"https://doi.org/10.1109/ACSD.2015.16","url":null,"abstract":"Traditional hierarchical modelling methods tend to have layers of abstraction corresponding to naturally existing layers of concern in multi-level systems. Although logically and functionally intuitive, this is not always optimal for analysis and design. For instance, parts of a system in the same logical layer may not contribute to the same degree on some metric, e.g. system power consumption. When focusing on a specific parameter or set of parameters, to moderate the analysis, design and runtime effort, less significant parts of the system should be modelled at higher levels of abstraction and more significant ones with more detail. This parametric significance-driven modelling approach focuses more on optimal parametric fidelity than on logical intuition. Using system power consumption as an example parameter, this paper presents Order Graphs (OGs), which have a clear hierarchical structure, and provide straightforward vertical zooming across multiple layers (orders) of model abstraction, resulting in the discovery of power-proportional cuts that run through different orders to be analysed together in a flat manner. Stochastic Activity Networks (SANs), a good flat modelling method, is suggested as an example of studying techniques for cuts discovered with OGs. A series of experiments on an Odroid development system consisting of an ARM big.LITTLE multi-core structure provides initial validation for the approach.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"19 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"When Do We (Not) Need Complex Assume-Guarantee Rules?","authors":"Antti Siirtola, S. Tripakis, Keijo Heljanko","doi":"10.1145/3012280","DOIUrl":"https://doi.org/10.1145/3012280","url":null,"abstract":"Assume-guarantee (AG) reasoning is a compositional verification method where a verification task involving many processes is broken into multiple verification tasks involving fewer and/or simpler processes. Unfortunately, AG verification rules, and especially circular rules are often complex and hence hard to reason about. This raises the question whether complex rules are really necessary, especially in view of formalisms that already enable compositional reasoning via simple rules based on precongruence. This paper investigates this question for two formalisms: (1) labelled transition systems (LTS) with parallel composition and weak simulation, and (2) interface automata (IA) with composition and alternating simulation ><;OI. In (1), not all AG rules are sound and the precongruence rule cannot replace all sound ones, but we can provide a generic and sound AG rule that complements the precongruence rule. We show that in (2) all AG rules are sound and can be replaced by a simple rule where all premisses are of the form Pi><;OI Qt. Moreover, we show that proofs in the LTS AG rule can be converted into proofs in the simple IA rule. This suggests that circular reasoning is a built-in feature of the IA formalism, and provided system components can be modelled as IA, complex assume-guarantee rules are not needed.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121518370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hernán Ponce de León, Olli Saarikivi, Kari Kähkönen, Keijo Heljanko, J. Esparza
{"title":"Unfolding Based Minimal Test Suites for Testing Multithreaded Programs","authors":"Hernán Ponce de León, Olli Saarikivi, Kari Kähkönen, Keijo Heljanko, J. Esparza","doi":"10.1109/ACSD.2015.12","DOIUrl":"https://doi.org/10.1109/ACSD.2015.12","url":null,"abstract":"This paper focuses on the problem of computing the minimal test suite for a terminating multithreaded program that covers all its executable statements. We have in previous work shown how to use unfoldings to capture the true concurrency semantics of multithreaded programs and to generate test cases for it. In this paper we rely on this earlier work and show how the unfolding can be used to generate the minimal test suite that covers all the executable statements of the program. The problem of generating such a minimal test suite is shown to be NP-complete in the size of the unfolding, and as a side result, covering executable transitions of any terminating safe Petri net is also NP-complete in the size of its unfolding. We propose SMT-encodings to these problems and give initial results on applying this encoding to compute the minimal test suite for several benchmarks.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127270762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testing Preorders for dMTS: Deadlock- and the New Deadlock/Divergence-Testing","authors":"Ferenc Bujtor, Lev Sorokin, W. Vogler","doi":"10.1109/ACSD.2015.21","DOIUrl":"https://doi.org/10.1109/ACSD.2015.21","url":null,"abstract":"Testing preorders on component specifications ensure that replacing a specification by a refined one does not introduce unwanted behaviour in an overall system. Considering deadlocks as unwanted, the preorder can be characterized by a failure semantics on labelled transition systems (LTS). In previous work, we have generalized this to modal transition systems (MTS) with a new, MTS-specific idea. In the present paper, we generalize this idea further to dMTS, a subclass of disjunctive MTS. On the one hand, the testing preorder can be characterized by the same failure semantics, and dMTS have no additional expressivity in our setting. On the other hand, the technical treatment is significantly harder and, surprisingly, the preorder is not a precongruence for parallel composition. Furthermore, we regard deadlocks and divergence as unwanted and characterize the testing preorder with an unusual failure-divergence semantics. This preorder is already on LTS strictly coarser - and hence better - than the traditional failuredivergence preorder. It is a precongruence on dMTS and much easier to handle than the deadlock-based preorder.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131681775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qi Tang, T. Basten, M. Geilen, S. Stuijk, Jibo Wei
{"title":"Task-FIFO Co-scheduling of Streaming Applications on MPSoCs with Predictable Memory Hierarchy","authors":"Qi Tang, T. Basten, M. Geilen, S. Stuijk, Jibo Wei","doi":"10.1145/3038484","DOIUrl":"https://doi.org/10.1145/3038484","url":null,"abstract":"Multi-processor systems-on-chips are widely adopted in implementing modern streaming applications to satisfy the ever increasing computing requirements. Predictable memory hierarchies, which make memory access predictable, can better satisfy the strict timing requirements of streaming applications. However, different levels of the memory hierarchy vary in latency and capacity. Hence, the system performance not only depends on the task schedule but also closely relates with the FIFO size distribution and FIFO allocation, which makes the scheduling problem much more complex. We propose an efficient Iteration-based Task-FIFO Co-Scheduling algorithm to optimize the FIFO size distribution and task/FIFO assignment. Randomly generated Synchronous Dataflow Graphs with different sizes and a set of practical applications are used to evaluate the performance of the proposed method. The experimental results demonstrate that the proposed algorithm outperforms the load balancing method and the Highest Access Frequency First algorithm.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132500505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Incremental Inductive Verification of Parameterized Timed Systems","authors":"Tobias Isenberg","doi":"10.1145/2984640","DOIUrl":"https://doi.org/10.1145/2984640","url":null,"abstract":"We propose an incremental workflow for the verification of parameterized systems modeled as symmetric networks of timed automata.Starting with a small number of timed automata in the network, a safety property is verified using IC3, a state-of-the-art algorithm based on induction.The result of the verification, an inductive strengthening, is reused proposing a candidate inductive strengthening for a larger network.If the candidate is valid, our main theorem states that the safety property holds for all sizes of the network of timed automata.Otherwise the number of automata is increased and the next iteration is started with a new run of IC3.We propose and thoroughly examine optimizations to our workflow, e.g. Feedback mechanisms to speed up the run of IC3.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130026678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Preserving Partial Order Runs in Parametric Time Petri Nets","authors":"É. André, T. Chatain, César Rodríguez","doi":"10.1145/3012283","DOIUrl":"https://doi.org/10.1145/3012283","url":null,"abstract":"Parameter synthesis for timed systems aims at deriving parameter valuations satisfying a given property. In this paper we target concurrent systems; it is well known that concurrency is a source of state-space explosion, and partial order techniques were defined to cope with this problem. Here we use partial order semantics for parametric time Petri nets as a way to significantly enhance the result of an existing synthesis algorithm. Given a reference parameter valuation, our approach synthesizes other valuations preserving, up to interleaving, the behavior of the reference parameter valuation. We show the applicability of our approach using acyclic asynchronous circuits.","PeriodicalId":162527,"journal":{"name":"2015 15th International Conference on Application of Concurrency to System Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}