Testing Preorders for dMTS: Deadlock- and the New Deadlock/Divergence-Testing

Abstract

Testing preorders on component specifications ensure that replacing a specification by a refined one does not introduce unwanted behaviour in an overall system. Considering deadlocks as unwanted, the preorder can be characterized by a failure semantics on labelled transition systems (LTS). In previous work, we have generalized this to modal transition systems (MTS) with a new, MTS-specific idea. In the present paper, we generalize this idea further to dMTS, a subclass of disjunctive MTS. On the one hand, the testing preorder can be characterized by the same failure semantics, and dMTS have no additional expressivity in our setting. On the other hand, the technical treatment is significantly harder and, surprisingly, the preorder is not a precongruence for parallel composition. Furthermore, we regard deadlocks and divergence as unwanted and characterize the testing preorder with an unusual failure-divergence semantics. This preorder is already on LTS strictly coarser - and hence better - than the traditional failuredivergence preorder. It is a precongruence on dMTS and much easier to handle than the deadlock-based preorder.