2021 Austrochip Workshop on Microelectronics (Austrochip)最新文献_第2页

Prototyping for a DDS-based I/Q reference signal generation on a capacitive sensing chip in 65nm CMOS using SystemC AMS, C HLS and VHDL 利用SystemC AMS, C HLS和VHDL在65nm CMOS电容传感芯片上实现基于dds的I/Q参考信号生成

2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576848

M. Bio, Harald Gietler, Josipa Plazonić, M. Ley, H. Zangl, W. Scherr

{"title":"Prototyping for a DDS-based I/Q reference signal generation on a capacitive sensing chip in 65nm CMOS using SystemC AMS, C HLS and VHDL","authors":"M. Bio, Harald Gietler, Josipa Plazonić, M. Ley, H. Zangl, W. Scherr","doi":"10.1109/austrochip53290.2021.9576848","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576848","url":null,"abstract":"Carrier frequency principles with synchronous de-modulation offer several advantages for use in capacitive sensors, in particular with respect to suppression of external disturbers, coexistence of sensors, and capability to determine frequency-dependent changes of the capacitance/impedance. A key component in such systems is the generation of the excitation signal(s) as well as the reference signals for demodulation.This work focuses on the early functional evaluation of direct digital synthesis for such signals using a virtual prototype in SystemC AMS (IEEE 1666.1), a high-level synthesis approach based on C (ISO 9899) as well as a classic hand-written VHDL code (IEEE 1076) for a rapid prototyping setup. The methods are compared with respect to efforts and results showing the advantages and disadvantages in a qualitative fashion. The lower efforts and lower risk of errors in the code provided by high level meta modeling allows to speed up the development cycle and required application dependent adaptations of signal generation in carrier frequency based capacitive sensor front-ends.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132536181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Static Digital Pre-Distortion Method for High-Speed Current-Steering Digital-to-Analog Converters 高速电流转向数模转换器的静态数字预失真方法

2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576860

Patrick Valet, D. Schwingshackl, Ulrich Gaier, A. Tonello

引用次数: 2

A 18-33 GHz Variable Gain Down-Conversion Mixer in 0.13µm SiGe:C BiCMOS technology 一种18-33 GHz可变增益下变频混频器，采用0.13µm SiGe:C BiCMOS技术

2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576885

Syed Sharfuddin Ahmed, H. Schumacher

{"title":"A 18-33 GHz Variable Gain Down-Conversion Mixer in 0.13µm SiGe:C BiCMOS technology","authors":"Syed Sharfuddin Ahmed, H. Schumacher","doi":"10.1109/austrochip53290.2021.9576885","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576885","url":null,"abstract":"This paper presents a high gain, high bandwidth (BW) variable gain downconversion mixer operating from 18-33 GHz RF frequency in the 0.13µm SiGe:C BiCMOS technology. The mixer core is based on micromixer topology, which needs a single-ended RF signal thus eliminating the need for additional balun at the input. The resistive loads were replaced by active PMOS loads with common-mode feedback (CMFB) resulting in higher conversion gain and low power consumption. The gain of the mixer is controlled by NMOS transistors operating as a variable resistor without any additional power consumption. Thus the variable-gain amplifier (VGA) can be eliminated from the receiver to reduce power consumption. The mixer gain ranges from -10 dB to 15.5 dB. Due to the elimination of the input balun and area consuming inductor, the mixer consumes a very small chip area of 310×216µm2 excluding the bond pads. The down-conversion mixer has a maximum input 1dB compression point (IP1dB) of -10 dBm, only limited by the linearity of the output buffer. The presented mixer provides high gain with variable gain function and moderate linearity while consuming a very small chip area compared to the state-of-the-art mixers in this frequency range.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A case study of BAG2 automized layout generation methodologies for a two-stage OTA in 28nm TSMC technology TSMC 28nm制程两阶段OTA中BAG2自动版图生成方法的案例研究

2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576866

Fatemeh Abbassi, M. Videnovic-Misic, M. Bashir, Feifei Zhang, T. Ostermann, G. Hueber

引用次数: 0

Keynote Austrochip 2021: Microelectronics – Quo Vadis?

2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576867

引用次数: 0

Noise Behaviour of EMI Improved Folded Cascode Amplifier Input Stages Including Layout Parasitics 包括布局寄生的EMI改进型折叠级联放大器输入级的噪声特性

2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576855

N. Czepl, Dominik Zupan

引用次数: 0