{"title":"Noise Behaviour of EMI Improved Folded Cascode Amplifier Input Stages Including Layout Parasitics","authors":"N. Czepl, Dominik Zupan","doi":"10.1109/austrochip53290.2021.9576855","DOIUrl":null,"url":null,"abstract":"In this paper we investigate the noise behaviour of electromagnetic interference (EMI) improved integrated folded cascode amplifier input stages. In this context we compare seven EMI improved differential input pair structures, using concepts of filtering, linearisation and compensation in terms of their noise behaviour. We pay special attention to the differences in the behaviour of the structures at the design stage and the layout stage, where we also considered layout-specific parasitics that can affect circuit and noise performance. We analyse the structures in terms of input referred noise, noise contribution of different devices, contributions of layout parasitics to noise, differential mode gain, gain-bandwidth product (GBWP) and power.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Austrochip Workshop on Microelectronics (Austrochip)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/austrochip53290.2021.9576855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper we investigate the noise behaviour of electromagnetic interference (EMI) improved integrated folded cascode amplifier input stages. In this context we compare seven EMI improved differential input pair structures, using concepts of filtering, linearisation and compensation in terms of their noise behaviour. We pay special attention to the differences in the behaviour of the structures at the design stage and the layout stage, where we also considered layout-specific parasitics that can affect circuit and noise performance. We analyse the structures in terms of input referred noise, noise contribution of different devices, contributions of layout parasitics to noise, differential mode gain, gain-bandwidth product (GBWP) and power.