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2021 Austrochip Workshop on Microelectronics (Austrochip)最新文献

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Analysis of TX-harmonics suppression in RF-DAC-based transmitters rf - dac发射机tx -谐波抑制分析
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576878
D. Hamidovic, P. Preyler, C. Preissl, M. Huemer, A. Springer
{"title":"Analysis of TX-harmonics suppression in RF-DAC-based transmitters","authors":"D. Hamidovic, P. Preyler, C. Preissl, M. Huemer, A. Springer","doi":"10.1109/austrochip53290.2021.9576878","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576878","url":null,"abstract":"In this paper we provide a mathematical description of up-conversion and digital-to-analog conversion in a radio-frequency digital-to-analog-converter (RF-DAC) and analyze harmonics appearing in the up-converted signal. We show a relation between the shape of the local oscillator (LO) signal and the amount of suppression of harmonics. Moreover, we propose a novel approach for increasing the sampling frequency in an RF-DAC without increasing the operational frequency and utilizing already existing analog components of the differential RF-DAC structure. Therewith, the even-order harmonics are additionally suppressed and the quantization noise around the carrier frequency is improved by 3 dB.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Message from the Organizing Committee Austrochip 2021 组委会寄语:Austrochip 2021
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576888
{"title":"Message from the Organizing Committee Austrochip 2021","authors":"","doi":"10.1109/austrochip53290.2021.9576888","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576888","url":null,"abstract":"","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124568810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Stacked C-DAC Output Stage with Feed-Forward Assisted Cascode Charging in 16 nm FinFET Technology 16纳米FinFET技术中前馈辅助级联充电的堆叠C-DAC输出级设计
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576874
Alessandra Cangianiello, Michael Kalcher, Daniel Gruber, M. Clara
{"title":"Design of a Stacked C-DAC Output Stage with Feed-Forward Assisted Cascode Charging in 16 nm FinFET Technology","authors":"Alessandra Cangianiello, Michael Kalcher, Daniel Gruber, M. Clara","doi":"10.1109/austrochip53290.2021.9576874","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576874","url":null,"abstract":"This paper presents the design and analysis of a stacked C-DAC output stage with feed-forward assisted cascode charging in 16 nm FinFET technology. The presented design operates with input signals in a frequency range from a few hundred MHz up to 6 GHz. Simulation results of the proposed design show that output power can be more than doubled compared to a reference design without stacked inverter while maintaining a SFDR over frequency of better than 65 dBc and two-tone intermodulation distortion of better than −68 dBc.The main linearity limit of the stacked inverter design is overcome by addition of a capacitive feed-forward branch.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Considerations on High-Performance Frequency Synthesizers and High-Q Oscillators 高性能频率合成器和高q振荡器的考虑
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576873
E. Hager, H. Pretl
{"title":"Considerations on High-Performance Frequency Synthesizers and High-Q Oscillators","authors":"E. Hager, H. Pretl","doi":"10.1109/austrochip53290.2021.9576873","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576873","url":null,"abstract":"Frequency generation is an important application in today’s radio frequency (RF) circuit design, especially for RF transceivers. The main challenges are to provide high spectral purity, while keeping the power consumption and area of the system low. In addition, with emerging mobile communication standards e.g. long term evolution (LTE) or 5G, various frequency bands and wide tuning ranges must be provided. This paper gives a brief overview of noise mechanisms, which have to be tackled, and a review of selected state-of-the-art frequency synthesizers (phase-locked-loops (PLLs)), as well as their limitations with respect to spectral purity. A novel interpretation of the figure-of-merit (FoM) for PLLs is shown emphasizing the impact of the resonators quality factor. In addition an outlook on possibilities to overcome the mentioned phase-noise limitations by using high quality factor (high-Q) RF-frequency generation circuit topologies utilizing e.g. surface-acoustic-wave- (SAW-), bulk-acoustic-wave- (BAW-) or micro-electro-mechanical-systems- (MEMS-) resonators.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121214264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
[Austrochip 2021 Front cover] [Austrochip 2021封面]
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576884
{"title":"[Austrochip 2021 Front cover]","authors":"","doi":"10.1109/austrochip53290.2021.9576884","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576884","url":null,"abstract":"","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Input/Output-Interlocking for Fault Mitigation in QDI Pipelines QDI管道中用于故障缓解的输入/输出联锁
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576871
Zaheer Tabassam, P. Behal, Robert Najvirt, A. Steininger
{"title":"Input/Output-Interlocking for Fault Mitigation in QDI Pipelines","authors":"Zaheer Tabassam, P. Behal, Robert Najvirt, A. Steininger","doi":"10.1109/austrochip53290.2021.9576871","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576871","url":null,"abstract":"In asynchronous quasi delay-insensitive (QDI) circuits, temporal masking is a serious concern because of their event-driven behavior, which makes them prone to environmental effects: Data acceptance windows, e.g. are defined by transitions (token/acknowledgement) alone, without temporal bounds, therefore a glitch occurring anytime throughout such a window cannot be distinguished from an expected, correct transition in a straightforward manner and hence threatens data integrity. Therefore, shortening that window is one proposed way in the literature to enhance temporal masking in QDI designs.We examine a variant of the Weak-Conditioned Half Buffer (WCHB) called Interlocking WCHB (which wisely shortens the transition window) because of its glitch filtering properties and a low cost implementation as compared to other variants. We propose modifications that enhance its dealing with illegal token words specifically when waiting for acknowledgment signal transitions in the so-called bubble limited operation mode. A very strict triple-check input filter with a glitch filter preventing the buffer from capturing an illegal state is used, which also enhances the deadlocking rate of the circuitry.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122089877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network 利用寄生效应设计一个基于倒装集成变压器的匹配网络
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576876
Pankaj Venuturupalli, S. Mahani, Sondón Santiago Martin, F. Kuttner, J. Sturm
{"title":"Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network","authors":"Pankaj Venuturupalli, S. Mahani, Sondón Santiago Martin, F. Kuttner, J. Sturm","doi":"10.1109/austrochip53290.2021.9576876","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576876","url":null,"abstract":"This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"43 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125890348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Copyright notice] (版权)
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576859
{"title":"[Copyright notice]","authors":"","doi":"10.1109/austrochip53290.2021.9576859","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576859","url":null,"abstract":"","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"4 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128808832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Tutorial Austrochip 2021: IC design using open source tools 教程Austrochip 2021:使用开源工具进行IC设计
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576865
Matt Venn
{"title":"Tutorial Austrochip 2021: IC design using open source tools","authors":"Matt Venn","doi":"10.1109/austrochip53290.2021.9576865","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576865","url":null,"abstract":"Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. In this tutorial we will take a look at the current state of the open source EDA tooling and then use them to build a small demonstration chip. The chip will be prepared for fabrication with Skywater's 130nm process, and take advantage of the free Google shuttles. There will be time for Q&A after the demonstration.","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130823048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Patrons Austrochip 2021
2021 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2021-10-14 DOI: 10.1109/austrochip53290.2021.9576858
{"title":"Patrons Austrochip 2021","authors":"","doi":"10.1109/austrochip53290.2021.9576858","DOIUrl":"https://doi.org/10.1109/austrochip53290.2021.9576858","url":null,"abstract":"","PeriodicalId":160147,"journal":{"name":"2021 Austrochip Workshop on Microelectronics (Austrochip)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122733676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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