Design of a Stacked C-DAC Output Stage with Feed-Forward Assisted Cascode Charging in 16 nm FinFET Technology

Abstract

This paper presents the design and analysis of a stacked C-DAC output stage with feed-forward assisted cascode charging in 16 nm FinFET technology. The presented design operates with input signals in a frequency range from a few hundred MHz up to 6 GHz. Simulation results of the proposed design show that output power can be more than doubled compared to a reference design without stacked inverter while maintaining a SFDR over frequency of better than 65 dBc and two-tone intermodulation distortion of better than −68 dBc.The main linearity limit of the stacked inverter design is overcome by addition of a capacitive feed-forward branch.