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Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing最新文献

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Orthogonal transpose-RAM cell array architecture with alternate bit-line to bit-line contact scheme 正交转置- ram单元阵列结构，具有位线到位线交替接触方案
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2001-08-06 DOI: 10.1109/MTDT.2001.945222
Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee
{"title":"Orthogonal transpose-RAM cell array architecture with alternate bit-line to bit-line contact scheme","authors":"Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee","doi":"10.1109/MTDT.2001.945222","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945222","url":null,"abstract":"An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line to bit-line contact scheme in the orthogonal RAM cell array architecture leads to asymmetric bit-line sensing scheme and (i, 2i) bit-line transposing scheme, and results in fast response time of the sense amplifier and low power dissipation for restoring.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
BIST-based bitfail mapping of an embedded DRAM 基于bist的嵌入式DRAM位失败映射
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2001-08-06 DOI: 10.1109/MTDT.2001.945225
Brian R. Kessler, J. Dreibelbis, Tim McMahon, Joshua S. McCloy, R. Kho
{"title":"BIST-based bitfail mapping of an embedded DRAM","authors":"Brian R. Kessler, J. Dreibelbis, Tim McMahon, Joshua S. McCloy, R. Kho","doi":"10.1109/MTDT.2001.945225","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945225","url":null,"abstract":"Trends in system-on-a-chip (SOC) semiconductor design and fabrication have complicated many well-established test processes. Circuits such as DRAM memories, which have been tested for decades on dedicated memory testers, using sophisticated test programs and patterns, may no longer be testable with such established methodologies. Testing and diagnosing embedded DRAM (eDRAM) memories is no less important in an SOC model than it was in a discrete DRAM model. In this paper we describe and evaluate a technique for doing bitfail-map-based diagnostics of an eDRAM, and demonstrate success in physical failure analysis (PFA).","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129859283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A P1500 compliant programmable BistShell for embedded memories 一个P1500兼容的可编程BistShell嵌入式存储器
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2001-08-06 DOI: 10.1109/MTDT.2001.945224
S. Koranne, T. Waayers, R. Beurze, C. Wouters, Sunil Kumar, G. S. Visweswara
{"title":"A P1500 compliant programmable BistShell for embedded memories","authors":"S. Koranne, T. Waayers, R. Beurze, C. Wouters, Sunil Kumar, G. S. Visweswara","doi":"10.1109/MTDT.2001.945224","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945224","url":null,"abstract":"We describe the design and implementation of an IEEE P1500 compliant programmable BIST for embedded memories. The proposed design can be embedded in other cores or systems with minimum test generation or test application overhead. The programmability of our BIST is useful when the algorithm is being refined while the memory architecture is under production. A variety of test algorithms can be implemented with the programmability provided in our design with no change to the BIST hardware. As an example we demonstrate the implementation of an algorithm to detect open decoder faults. This example is shown for its didactic content as it brings out the programmable axis of our design. Our design also offers means to perform dedicated delay tests as well as scan tests for diagnosis. We show by synthesis experiments that the extra area cost for the BIST hardware is relatively small for medium to large memories.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130898559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Equivalence checking a 256 MB SDRAM 等效性检查一个256 MB的SDRAM
Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 2001-08-06 DOI: 10.1109/MTDT.2001.945234
S. Napper, D. Yang
{"title":"Equivalence checking a 256 MB SDRAM","authors":"S. Napper, D. Yang","doi":"10.1109/MTDT.2001.945234","DOIUrl":"https://doi.org/10.1109/MTDT.2001.945234","url":null,"abstract":"This paper outlines how symbolic simulation was used to verify both data and sequence integrity in a 256 MB SDRAM. The initial step is to examine the underlying equivalence-checking engine and then explain how it is applied to SDRAM verification. SDRAM verification is interesting in that it captures both memory and sequence verification. The data integrity verification is valid for any type of memory structure and the sequence integrity can be extended to many types of sequenced machines.","PeriodicalId":159230,"journal":{"name":"Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115389695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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