BIST-based bitfail mapping of an embedded DRAM

Abstract

Trends in system-on-a-chip (SOC) semiconductor design and fabrication have complicated many well-established test processes. Circuits such as DRAM memories, which have been tested for decades on dedicated memory testers, using sophisticated test programs and patterns, may no longer be testable with such established methodologies. Testing and diagnosing embedded DRAM (eDRAM) memories is no less important in an SOC model than it was in a discrete DRAM model. In this paper we describe and evaluate a technique for doing bitfail-map-based diagnostics of an eDRAM, and demonstrate success in physical failure analysis (PFA).