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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)最新文献

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Post-placement pin optimization 放置后引脚优化
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.57
J. Westra, P. Groeneveld
{"title":"Post-placement pin optimization","authors":"J. Westra, P. Groeneveld","doi":"10.1109/ISVLSI.2005.57","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.57","url":null,"abstract":"Pin assignment is the process of placing pins on the boundary of a chip or macro during chip design. Problem is that cell placement and pin assignment form a chicken and egg problem: cell placement needs pin positions, while pin positions should be optimally adapted to the placement of cells. The contributions of this paper are threefold. First, the chicken and egg problem is tackled using the observation that pin positions mainly influence cell positions on the periphery of the circuit. A first placement run is used to place the \"core\" of the circuit followed by adapting pin positions such that wire length of the periphery of the circuit can be optimized. The second contribution is that pin assignment issues that arise in a hierarchical flow, where pins serve as connections between two hierarchical levels, can be incorporated. The final contribution is that the tedious process of manual \"fiddling around\" with pins in order to reduce congestion is automated through pin constraints set by the designer. Experimental evidence on a large benchmark suite with large designs shows that our method is effective. On average a significant 2.55% reduction in total wire length is achieved. For congested designs, such a reduction can make the difference between routable and not routable. This reduction is due to actual restructuring of the placement, showing the validity of the assumptions. The proposed methods are easily incorporated in common physical design flows.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133892787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs 基于VCSELs光学系统的光差分可重构门阵列
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.54
M. Miyano, Minoru Watanabe, F. Kobayashi
{"title":"Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs","authors":"M. Miyano, Minoru Watanabe, F. Kobayashi","doi":"10.1109/ISVLSI.2005.54","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.54","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs) have been developed to allow rapid reconfiguration. We have developed an optically differential reconfigurable gate array (ODRGA) to realize fast and arbitrary partial reconfiguration capabilities. This paper presents the structure of a fabricated ODRGA-VLSI chip using an optical system with vertical cavity surface emitting lasers (VCSELs) along with experimental results of reconfiguration","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Energy efficient architectures for the log-MAP decoder through intelligent memory usage 通过智能内存使用的log-MAP解码器的节能架构
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.29
I. Atluri, A. K. Kumaraswamy
{"title":"Energy efficient architectures for the log-MAP decoder through intelligent memory usage","authors":"I. Atluri, A. K. Kumaraswamy","doi":"10.1109/ISVLSI.2005.29","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.29","url":null,"abstract":"Turbo decoding generally employs maximum a posteriori (MAP) and the soft output Viterbi (SOVA) algorithm in its soft-input soft-output (SISO) component decoders. This paper reformulates the implementation of a low power Log-MAP decoder with reduced storage requirement and based on the optimized MAP algorithm that calculates the reverse state metrics in the forward recursive manner. As a result, the authors present new low power derivatives of this decoder through a variation in the percentage of memory savings. Three low power architectures of the Log-MAP decoder not employing the sliding window technique have been developed and post layout power savings of approximately 44%, 40% and 36% with respect to the conventional implementation have been observed.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133336754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Increasing data TLB resilience to transient errors 增加数据TLB对瞬态错误的弹性
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.43
Feihui Li, M. Kandemir
{"title":"Increasing data TLB resilience to transient errors","authors":"Feihui Li, M. Kandemir","doi":"10.1109/ISVLSI.2005.43","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.43","url":null,"abstract":"This paper first demonstrates that a large fraction of data TLB entries are dead (i.e., not used again before being replaced) for many applications at any given time during execution. Based on this observation, it then proposes two alternate schemes that replicate actively accessed data TLB entries in these dead entries to increase the resilience of the TLB against transient errors.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129297755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A hierarchical method for wiring congestion prediction 线路拥塞预测的分层方法
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.6
Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, M. Gu, Jiaguang Sun
{"title":"A hierarchical method for wiring congestion prediction","authors":"Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, M. Gu, Jiaguang Sun","doi":"10.1109/ISVLSI.2005.6","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.6","url":null,"abstract":"Interconnect congestion estimation plays an important role in the physical design of integrated circuits. This paper presents a novel probabilistic approach to predicting wiring space in two-dimensional arrays. We propose a hierarchical estimation method to derive approximated upper bounds for wiring space. We use the net density distribution for predicting the routing congestion. Experimental results demonstrate the promising performance of the new approach.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"465 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS realization of online testable reversible logic gates 可在线测试可逆逻辑门的CMOS实现
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.23
D. Vasudevan, P. Lala, J. Parkerson
{"title":"CMOS realization of online testable reversible logic gates","authors":"D. Vasudevan, P. Lala, J. Parkerson","doi":"10.1109/ISVLSI.2005.23","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.23","url":null,"abstract":"Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115936370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
IR drop and ground bounce awareness timing model 红外跌落和地面反弹感知时序模型
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.44
Muzhou Shao, Youxin Gao, L. Yuan, Martin D. F. Wong
{"title":"IR drop and ground bounce awareness timing model","authors":"Muzhou Shao, Youxin Gao, L. Yuan, Martin D. F. Wong","doi":"10.1109/ISVLSI.2005.44","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.44","url":null,"abstract":"As the IC technology scales down, the effect of IR drop/ground bounce becomes increasingly significant. IR drop and ground bounce can compromise the gate driving capability and degrade the IC performance, and even can make IC functional failures. Hence, it is crucial to capture this effect efficiently and accurately in order to improve circuit reliability. In this paper, we proposed a timing model with consideration of IR drop and ground bounce. Our model can be derived directly from the existing timing tables (e.g. Synopsys.db or CLF tables), which are used in normal timing analysis. Compared with the traditional k-factor approach, our method does not require SPICE netlist and SPICE simulations. Moreover, the accuracy of our model is better than k-factor approach.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132413405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Jitter in deep sub-micron interconnect 深亚微米互连中的抖动
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.45
Jinwook Jang, Sheng Xu, W. Burleson
{"title":"Jitter in deep sub-micron interconnect","authors":"Jinwook Jang, Sheng Xu, W. Burleson","doi":"10.1109/ISVLSI.2005.45","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.45","url":null,"abstract":"Timing jitter in long on-chip interconnects has become an increasingly important issue in signal integrity and timing violations. In this paper, we focus on cycle-to-cycle jitter induced by repeater power supply noise in both point-to-point and branched RC and RLC interconnects in 70nm CMOS. We develop an analytical expression for jitter based on propagation delay variation that accurately predicts HSPICE simulation results. We show the difference in impact between RC and RLC wire models on jitter (up to 64%). We also show a method for jitter-optimal repeater insertion which differs from conventional delay optimal insertion methods, resulting in larger repeaters. Finally, we introduce methods which can decrease timing violations in branched global interconnects by adjusting repeater size and tuning the phase of the power supply noise.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"14 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132545732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A low power embedded dataflow coprocessor 低功耗嵌入式数据流协处理器
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.9
Yijun Liu, S. Furber
{"title":"A low power embedded dataflow coprocessor","authors":"Yijun Liu, S. Furber","doi":"10.1109/ISVLSI.2005.9","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.9","url":null,"abstract":"Power consumption has become one of the most important concerns in microprocessor design. However, the potential for further power-saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative way is proposed in this paper to save power - embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments very efficiently. The primary experimental results show that the dataflow coprocessor can increase the power efficiency of a RISC processor by an order of magnitude.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient diagrams 基于元素系数图的多参数灵敏度分析快速模拟电路合成
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.33
Huiying Yang, Anuradha Agarwal, R. Vemuri
{"title":"Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient diagrams","authors":"Huiying Yang, Anuradha Agarwal, R. Vemuri","doi":"10.1109/ISVLSI.2005.33","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.33","url":null,"abstract":"This paper presents a new method to perform efficient analog circuit synthesis by using accurate multiparameter sensitivity analysis based on element-coefficient diagrams (ECDs). An ECD is the cancellation-free and per-coefficient term generation version of determinant decision diagrams (DDDs). The techniques based on DDD are the fastest symbolic analysis algorithms reported so far in literature. The symbolic multiparameter sensitivity equations obtained from ECDs can be evaluated so as to tune the parameters in analog synthesis process efficiently. The proposed methodology has been applied for the synthesis of a two stage opamp circuit. The experimental results demonstrate that the speed and convergence of analog synthesis are improved significantly.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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