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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)最新文献

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A high speed reconfigurable gate array for gigahertz applications 用于千兆赫应用的高速可重构门阵列
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.8
Jong-Ru Guo, C. You, M. Chu, Okan Erdogan, R. Kraft, J. McDonald
{"title":"A high speed reconfigurable gate array for gigahertz applications","authors":"Jong-Ru Guo, C. You, M. Chu, Okan Erdogan, R. Kraft, J. McDonald","doi":"10.1109/ISVLSI.2005.8","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.8","url":null,"abstract":"This paper describes the implementation of the next generation of a scalable SiGe FPGA in the latest IBM 8HP SiGe process (fT = 210GHz) that serves as an interleaving and de-interleaving block in a high speed reconfigurable data acquisition system. In this paper, different generations of SiGe configurable blocks (basic cells) are presented and measured. The latest generation has a 94% reduction in power consumption (from 71mW to 4.2mW) and an 83% reduction of the propagation delay (from 238ps to 42ps) compared to the first generation design. To demonstrate the SiGe FPGA's capabilities of handling GHz signals, the SiGe FPGAs are configured as a multiplexer (MUX), de-multiplexer (DEMUX) and pseudo-SERDES. For the IBM 8HP process, the MUX, DEMUX and pseudo-SERDES can achieve a transmission rate of 28Gbps. For the previous IBM 7HP case, the 4:1 multiplexer runs at a transmission rate of 8Gbps. With these design results, the SiGe FPGA is able to process GHz signals such as S and K microwave bands.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sensitivity analysis of a cluster-based interconnect model for FPGAs 基于簇的fpga互连模型灵敏度分析
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.68
R. Huang, R. Vemuri
{"title":"Sensitivity analysis of a cluster-based interconnect model for FPGAs","authors":"R. Huang, R. Vemuri","doi":"10.1109/ISVLSI.2005.68","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.68","url":null,"abstract":"Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interconnect model on a set of key architectural parameters. The evaluations show that the analyzed structure is not only insensitive to the various parameters for the formulation of that architecture, but also admits more designs with potential high performance improvement.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124116034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
System level methodology for programming CMP based multi-threaded network processor architectures 基于多线程网络处理器体系结构的CMP编程系统级方法
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.71
Vijay Ramamurthi, J.M. McCollum, Christopher Ostler, Karam S. Chatha
{"title":"System level methodology for programming CMP based multi-threaded network processor architectures","authors":"Vijay Ramamurthi, J.M. McCollum, Christopher Ostler, Karam S. Chatha","doi":"10.1109/ISVLSI.2005.71","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.71","url":null,"abstract":"The increasing demand for programmable platforms that enable high bandwidth communication traffic processing has led to the advent of chip multi-processor (CMP) based multi-threaded network processor (NP) architectures. The CMP based architectures include a multitude of heterogeneous memory units ranging from on-chip register banks, local data memories, and scratch pads to multiple banks of off-chip SRAM and DRAM. Implementation of applications on such complex CMP architectures involves mapping of functionality on processing units, and mapping of data items on the memory units with an objective of maximizing the throughput. This paper presents a system-level methodology that consists of a programming model and optimization techniques for solving the functionality and memory mapping problem on CMP based multi-threaded NP architectures. The proposed techniques are evaluated by implementing three representative NP applications on the Intel IXP2400 processor which belongs to the class of CMP based multi-threaded architectures.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127885866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A scalable parallel SoC architecture for network processors 一个可扩展的并行SoC架构的网络处理器
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.13
Jörg-Christian Niemann, Mario Porrmann, U. Rückert
{"title":"A scalable parallel SoC architecture for network processors","authors":"Jörg-Christian Niemann, Mario Porrmann, U. Rückert","doi":"10.1109/ISVLSI.2005.13","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.13","url":null,"abstract":"Information processing and networking of technical devices find their way into our daily life. In order to process the continuously growing quantity of data, powerful communication nodes for network processing are needed. We present an architecture for network processors that is based on a uniform, massively parallel structure. Thus, our approach takes advantage of reusing predefined IP building blocks. This leads to a short time to market, a high reliability and a scalable architecture. Our architecture is scalable to different areas of application by varying the number of integrated processors. Additionally, specific hardware accelerators can be embedded, which are optimized for the target application, in order to be especially resource-efficient in respect to power consumption, computational power and required area.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115866159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
12-23 GHz ultra wide tuning range voltage-controlled ring oscillator with hybrid control schemes 采用混合控制方案的12-23 GHz超宽调谐范围压控环形振荡器
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.1
Y. U. Yim, J. McDonald, R. Kraft
{"title":"12-23 GHz ultra wide tuning range voltage-controlled ring oscillator with hybrid control schemes","authors":"Y. U. Yim, J. McDonald, R. Kraft","doi":"10.1109/ISVLSI.2005.1","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.1","url":null,"abstract":"This paper presents the design of a voltage-controlled ring oscillator that has ultra wide tuning range of 12 to 23 GHz with hybrid control schemes. The voltage-controlled oscillator (VCO) uses a feedforward interpolation topology scheme and a varactor diode load capacitance variation scheme to control the oscillation. The measurement result of the VCO shows good linearity in frequency-voltage characteristics over the ultra wide tuning range.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116884234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Lemma exchange in a microcontroller based parallel SAT solver 基于微控制器的并行SAT求解器引理交换
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.47
Tobias Schubert, B. Becker
{"title":"Lemma exchange in a microcontroller based parallel SAT solver","authors":"Tobias Schubert, B. Becker","doi":"10.1109/ISVLSI.2005.47","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.47","url":null,"abstract":"We present a new and more powerful variant of our distributed SAT procedure for microchip PIC microcontrollers. The algorithm is an adaption of the state-of-the-art solver CHAFF optimised for the limited resources of the microchip processors. It contains features of modern SAT engines like conflict-driven learning and nonchronological backtracking as well as an efficient work stealing method to run several processors in parallel. The underlying hardware environment is a special multiprocessor system based on a PC ISA slot card holding up to 9 PIC microcontrollers. Thereby the communication topology between the computing units can be reconfigured during runtime. In this work we focus on what is sometimes called lemma exchange in the literature: the possibility to exchange useful information (conflict clauses / lemmas) between processors working on different parts of the search tree of the same problem instance. Besides technical aspects we also analyse the speedup obtained by lemma exchange and describe the effects observed during our experiments.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115397820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new organization for a perceptron-based branch predictor and its FPGA implementation 一种基于感知器的分支预测器结构及其FPGA实现
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.11
O. Cadenas, G. Megson, Daniel Jones
{"title":"A new organization for a perceptron-based branch predictor and its FPGA implementation","authors":"O. Cadenas, G. Megson, Daniel Jones","doi":"10.1109/ISVLSI.2005.11","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.11","url":null,"abstract":"An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"961 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127033929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Balancing system level pipelines with stage voltage scaling 用级电压缩放平衡系统级管线
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.20
Hui Guo, S. Parameswaran
{"title":"Balancing system level pipelines with stage voltage scaling","authors":"Hui Guo, S. Parameswaran","doi":"10.1109/ISVLSI.2005.20","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.20","url":null,"abstract":"This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in throughput and response time, and 11% improvement in power consumption can be achieved with limited memory overhead.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129738256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low cost test vector compression/decompression scheme for circuits with a reconfigurable serial multiplier 具有可重构串行乘法器电路的低成本测试矢量压缩/解压缩方案
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.49
Avijit Dutta, Terence Rodrigues, N. Touba
{"title":"Low cost test vector compression/decompression scheme for circuits with a reconfigurable serial multiplier","authors":"Avijit Dutta, Terence Rodrigues, N. Touba","doi":"10.1109/ISVLSI.2005.49","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.49","url":null,"abstract":"Many chip designs contain one or more serial multipliers. A scheme is proposed to exploit this to compress the amount of data that needs to be stored on the tester and transferred to the CUT during manufacturing test. The test vectors are stored on the tester in a compressed format by expressing each test vector as a product of two numbers. While performing multiplication on these stored seeds in the Galois field modulo 2, GF(2), the multiplier states (i.e. the partial products) are tapped to reproduce the test vectors and fill the scan chains. In contrast with other test vector decompression schemes that add significant test specific hardware to the chip, the proposed scheme reduces hardware overhead by making use of existing functional circuitry. Experimental results demonstrate that a high encoding efficiency can be achieved using the proposed scheme.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of incremental communication for multilayer neural networks on a field programmable gate array 基于现场可编程门阵列的多层神经网络增量通信分析
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.18
J. R. Dick, K. Kent
{"title":"Analysis of incremental communication for multilayer neural networks on a field programmable gate array","authors":"J. R. Dick, K. Kent","doi":"10.1109/ISVLSI.2005.18","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.18","url":null,"abstract":"A neural network is a massively parallel distributed processor made up of simple processing units known as neurons. These neurons are organized in layers and every neuron in each layer is connected to each neuron in the adjacent layers. This connection architecture makes for an enormous number of communication links between neurons This is a major issue when considering a hardware implementation of a neural network since communication links take up hardware space, and hardware space costs money. To overcome this space problem incremental communication for multilayer neural networks has been proposed. Incremental communication works by only communicating the change in value between neurons as opposed to the entire magnitude of the value. This allows for the numbers to be represented with a fewer number of bits, and thus can be communicated with narrower communication links. To validate the idea of incremental communication an incremental communication neural network was designed and implemented, and then compared to a traditional neural network. From the implementation it is seen that even though the incremental communication neural network saves design space through reduced communication links, the additional resources necessary to shape the data for transmission outweighs any design space savings when targeting a modern FPGA.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128430807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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