一种基于感知器的分支预测器结构及其FPGA实现

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.11

O. Cadenas, G. Megson, Daniel Jones

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引用次数: 11

摘要

将基于神经网络的预测器的原始计算在算法层面上进行不变的重排，作为一种新的组织形式。它的FPGA实现产生的电路比原始算法的直接实现快1.7。这个更快的时钟速率允许使用几乎相同的硬件预算实现具有更长的历史长度的预测器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new organization for a perceptron-based branch predictor and its FPGA implementation

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

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来源期刊

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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