CMOS realization of online testable reversible logic gates

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.23

D. Vasudevan, P. Lala, J. Parkerson

引用次数: 13

Abstract

Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.

查看原文本刊更多论文

可在线测试可逆逻辑门的CMOS实现

提出了三种可用于实现不同复杂程度的可逆数字电路的可逆逻辑门。这些门的主要特点是它们为使用它们实现的电路提供在线可测试性。本文介绍了这些门的CMOS实现方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

自引率

0.00%

发文量