2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献_第3页

Classification and transformation of dynamic dataflow programs 动态数据流程序的分类与转换

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706280

M. Wipliez, M. Raulet

引用次数: 35

Real-time classification based on color and texture attributes on an FPGA-based architecture 基于fpga架构的颜色和纹理属性实时分类

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706272

M. Ibarra-Manzano, M. Devy, J. Boizard

{"title":"Real-time classification based on color and texture attributes on an FPGA-based architecture","authors":"M. Ibarra-Manzano, M. Devy, J. Boizard","doi":"10.1109/DASIP.2010.5706272","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706272","url":null,"abstract":"The design and the implementation of algorithms on FPGA-based architectures, is a complex task, above all for image processing. Many vision applications (video monitoring, obstacle detection from a vehicle) require real time performance. This paper analyzes only a classical function involved in these applications: pixel characterization by an attribute vector, and pixel classification as belonging or not to an interest class. Typical attributes are color and texture. Color is described by the chrominance given by the a and b coordinates in the CIE-Lab color space. Texture is only computed from the L* coordinate, describing the local intensity variations in a neighborhood of every pixel. AdaBoost has been selected in order to learn how to classify every pixel from its attribute vector. From a learning data base, it is learnt off line how to select and combine a given number of weak classifiers; then, the classifier parameters are loaded on an FPGA-based kit. This paper proposes different architectures and presents some results obtained from images acquired from a robot, in order to classify a pixel as Ground or Obstacle.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133121494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

GPU implementation of motion estimation for visual saliency GPU实现的运动估计的视觉显著性

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706268

A. Rahman, D. Houzet, D. Pellerin, Lionel Agud

引用次数: 6

An inter-task real time DVFS scheme for multiprocessor embedded systems 多处理器嵌入式系统的任务间实时DVFS方案

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706257

Muhammad Khurram Bhatti, C. Belleudy, M. Auguin

{"title":"An inter-task real time DVFS scheme for multiprocessor embedded systems","authors":"Muhammad Khurram Bhatti, C. Belleudy, M. Auguin","doi":"10.1109/DASIP.2010.5706257","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706257","url":null,"abstract":"In this paper1, we have addressed energy-efficient scheduling of real time applications intended to be executed on multiprocessor systems. Our proposed technique, called Deterministic Stretch-to-Fit (DSF) technique, is based on inter-task real time dynamic voltage and frequency scaling (RT-DVFS). It mainly comprises of three components. Firstly, we propose an online algorithm to reclaim energy by adapting to the variations in actual workload of target application tasks. Secondly, we extend our online algorithm with an adaptive and speculative speed adjustment mechanism. This mechanism anticipates early completion of future task instances based on the information of their average workload. Thirdly, we propose a one-task extension technique for multi-task multiprocessor systems. No real time constraints of target application are violated while applying our proposed technique. Simulation results show that our online slack reclamation algorithm alone gives up to 53% gains on energy consumption and our extended speculative speed adjustment mechanism, along with the one-task extension technique, gives additional gains, reaching a theoretical low-bound on the scalable frequency and voltage.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117186303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems 多核嵌入式系统H.264/AVC编码器软硬件协同设计

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706271

T. Dias, N. Roma, L. Sousa

引用次数: 4

A flexible implementation of a Global Navigation Satellite System (GNSS) receiver for on-board satellite navigation 用于星载卫星导航的全球导航卫星系统(GNSS)接收机的灵活实现

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706284

Arnaud Dion, E. Boutillon, V. Calmettes, Emmanuel Liegon

引用次数: 6

A dynamically reconfigurable asynchronous processor for low power applications 用于低功耗应用的动态可重构异步处理器

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706249

Khodor Ahmad Fawaz, T. Arslan, S. Khawam, M. Muir, I. Nousias, Iain A. B. Lindsay, A. Erdogan

{"title":"A dynamically reconfigurable asynchronous processor for low power applications","authors":"Khodor Ahmad Fawaz, T. Arslan, S. Khawam, M. Muir, I. Nousias, Iain A. B. Lindsay, A. Erdogan","doi":"10.1109/DASIP.2010.5706249","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706249","url":null,"abstract":"There is an increasing demand in high-throughput mobile applications for programmability and energy efficiency. Conventional mobile Central Processing Units (CPUs) and Very Long Instruction Word (VLIW) processors cannot meet these demands. In this paper, we present a novel dynamically reconfigurable processor that targets these requirements. The processor consists of a heterogeneous array of coarse grain asynchronous cells. The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability via conventional high-level languages. When compared to an equivalent synchronous design, our processor results in a power reduction of up to 18%. Additionally, our processor delivers considerably lower power consumption when compared to a market leading VLIW and a low-power ARM processor, while maintaining their throughput performance. Our processor resulted in a reduction in power consumption over the ARM7 processor of around 9.5 times when running the bilinear demosaicing algorithm at the same throughput.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122488797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On-chip compression for HDR image sensors 片上压缩HDR图像传感器

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706262

F. G. Messaoud, A. Peizerat, A. Dupret, Y. Blanchard

引用次数: 11

A Roadmap for Autonomous Fault-Tolerant Systems 自主容错系统的路线图

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706281

X. Iturbe, K. Benkrid, T. Arslan, I. Martinez, M. Azkarate-askasua, M. Santambrogio

引用次数: 23

Architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology 基于标准CMOS技术的纳秒级分辨率集成条纹相机的结构和信号重建方法

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706279

M. Zlatanski, W. Uhring, Virginie Zint, J. L. Normand, D. Mathiot

{"title":"Architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology","authors":"M. Zlatanski, W. Uhring, Virginie Zint, J. L. Normand, D. Mathiot","doi":"10.1109/DASIP.2010.5706279","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706279","url":null,"abstract":"This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from the chip raw data. Two main ISC architectures are presented. The first adopts the traditional for the most silicon imagers pixel array configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a Conventional Streak Camera (CSC), coupled to an amplifier stage and an analog sampling and storage unit. For both architectures, depending on the on-chip processing of the photocharges, appropriate signal reconstruction techniques are required in order to restore the luminous signal shape. A novel single vector ISC front-end architecture with an asynchronous photodiode reset scheme is presented. Algorithms allowing the luminous event reconstruction are proposed and validated through simulations for all the ISCs considered.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125178309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1