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2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献

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Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation 自动生成高效的MPEG-4可重构视频编码解码器实现
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706274
Ruirui Gu, J. Piat, M. Raulet, J. Janneck, S. Bhattacharyya
{"title":"Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation","authors":"Ruirui Gu, J. Piat, M. Raulet, J. Janneck, S. Bhattacharyya","doi":"10.1109/DASIP.2010.5706274","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706274","url":null,"abstract":"This paper proposes an automatic design flow from user-friendly design to efficient implementation of video processing systems. This design flow starts with the use of coarse-grain dataflow representations based on the CAL language, which is a complete language for dataflow programming of embedded systems. Our approach integrates previously developed techniques for detecting synchronous dataflow (SDF) regions within larger CAL networks, and exploiting the static structure of such regions using analysis tools in The Dataflow interchange format Package (TDP). Using a new XML format that we have developed to exchange dataflow information between different dataflow tools, we explore systematic implementation of signal processing systems using CAL, SDF-like region detection, TDP-based static scheduling, and CAL-to-C (CAL2C) translation. Our approach, which is a novel integration of three complementary dataflow tools — the CAL parser, TDP, and CAL2C — is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128840060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High speed Fp multipliers and adders on FPGA platform 基于FPGA平台的高速Fp乘法器和加法器
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 1900-01-01 DOI: 10.1109/DASIP.2010.5706241
Santosh K. Ghosh, Debdeep Mukhopadhyay, D. R. Chowdhury
{"title":"High speed Fp multipliers and adders on FPGA platform","authors":"Santosh K. Ghosh, Debdeep Mukhopadhyay, D. R. Chowdhury","doi":"10.1109/DASIP.2010.5706241","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706241","url":null,"abstract":"The paper proposes high speed FPGA implementations of adders and multipliers in Fp. The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments have been performed. The result shows that the proposed design provides 70% speedup from the best known designs.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132404863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
An FPGA softcore based implementation of a bird call recognition system for sensor networks 基于FPGA软核的传感器网络鸟叫声识别系统的实现
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 1900-01-01 DOI: 10.1109/DASIP.2010.5706238
Hongzhi Liu, N. Bergmann
{"title":"An FPGA softcore based implementation of a bird call recognition system for sensor networks","authors":"Hongzhi Liu, N. Bergmann","doi":"10.1109/DASIP.2010.5706238","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706238","url":null,"abstract":"To investigate the on-sensor processing capabilities of FPGAs, this paper presents a bird call recognition system based on linear predictive cepstral coefficients (LPCC) and dynamic time warping (DTW) algorithms for sensor network applications, and compares two different implementations on a Xilinx Spartan-3E FPGA with MicroBlaze soft processor. The experimental results show that compared to the software-only solution, the software / hardware (SW/HW) implementation with hardware coprocessor for DTW yields significant performance improvement by the factor of 13.8 and 33.4 respectively for two example inputs, and achieves about 31.1 times energy efficiency by using only 7.5% more power.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125985964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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