2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献_第4页

A portable Video Tool Library for MPEG Reconfigurable Video Coding using LLVM representation 一个便携式视频工具库，用于使用LLVM表示的MPEG可重构视频编码

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706263

J. Gorin, M. Wipliez, F. Prêteux, M. Raulet

{"title":"A portable Video Tool Library for MPEG Reconfigurable Video Coding using LLVM representation","authors":"J. Gorin, M. Wipliez, F. Prêteux, M. Raulet","doi":"10.1109/DASIP.2010.5706263","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706263","url":null,"abstract":"MPEG Reconfigurable Video Coding (RVC) represents the last answer of MPEG to overcome the lack of interoperability between codecs deployed in the market nowadays. The main goal of MPEG RVC is to provide a set of coding tools employed in all MPEG standards, the Video Tools Library (VTL), encapsulated into independent entities called Functional Units (FUs). FUs are described as dataflow actors in RVC-CAL actor language (RVC-CAL) and decoders are described as dataflow programs with the Abstract DecoderModels (ADMs). Therefore, an ADM of an MPEG decoder corresponds in MPEG RVC to a network of FUs taken from the VTL. The typical use of MPEG RVC is to translate an ADM into a hardware or software description language that target one specific platform. In [1], we propose to skip this synthesis process of ADM and to directly integrate a portable version of VTL described in the Low-Level Virtual Machine Intermediate Representation (LLVM IR) inside platforms. This portable VTL is couple with a new RVC Decoder, we called Just-In-Time Adaptive Decoder Engine (Jade), that dynamically instantiates ADM to decode any encoded video using its associated network description. In this paper, we introduce the different compiling steps required to obtain an automatically translation of a VTL described in RVC-CAL into a portable VTL described in LLVM. This translation is based on a new RVC-CAL compiler called Open RVC-CAL Compiler (Orcc).","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design 基于rvc - cal设计的粗粒度可重构硬件体系结构

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706259

Cecile Beaumin, O. Sentieys, E. Casseau, A. Carer

引用次数: 7

Design and hardware implementation of a low-complexity multiuser vector precoder 低复杂度多用户矢量预编码器的设计与硬件实现

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706260

M. Barrenechea, L. G. Barbero, M. Mendicute, J. Thompson

引用次数: 13

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding RVC-CAL数据流实现MPEG AVC/H.264CABAC解码

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706266

E. Bezati, M. Mattavelli, M. Raulet

引用次数: 17

Hardware code generation from dataflow programs 从数据流程序生成硬件代码

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706254

Nicolas Siret, M. Wipliez, J. Nezan, Aimad Rhatay

引用次数: 23

Wireless Sensor Network node global energy consumption modeling 无线传感器网络节点全球能耗建模

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706246

A. Courtay, A. Pegatoquet, M. Auguin, C. Chaabane

引用次数: 9

A case study of the stochastic modeling approach for range estimation 距离估计的随机建模方法的实例研究

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706256

A. Banciu, E. Casseau, D. Ménard, Thierry Michel

引用次数: 7

FPGA-based rectification of stereo images 基于fpga的立体图像校正

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706265

João G. P. Rodrigues, J. Ferreira

引用次数: 7

Low power noise detection circuit utilizing switching activity measurement method 采用开关活度测量法的低功耗噪声检测电路

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706273

Z. Razak, A. Erdogan, T. Arslan

{"title":"Low power noise detection circuit utilizing switching activity measurement method","authors":"Z. Razak, A. Erdogan, T. Arslan","doi":"10.1109/DASIP.2010.5706273","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706273","url":null,"abstract":"Noise often limits the performance of transmitted signals and degrades signals quality. Moreover, stochastic nature of noise makes it difficult to predict, and hence, is hard to detect. In hardware implementation, the reduction of noise can only be optimized in the baseband where complex and intensive computation is executed using digital signal processors (DSPs). Although analog pre-filtering is applied at receiver front-end to reduce interferences, fractions of noise still exist due to non-ideality of the device. We present a method to detect noise in signal using switching activity measurement (SWAM) of analog-to-digital converter (ADC) output. Simulation results show that switching activity of digital outputs varies with different signal-to-noise ratio (SNR) values where high SNR value leads to low switching activity. A noise detection unit (NDU) is implemented and is synthesized using AMS 0.35µm/3.3V CMOS standard library. The result shows minimum overhead where NDU occupies only 774 equivalent 2-input NAND gates and consumes only 978µW of power. With advantage of small complexity and power usage, NDU is attractive to be used in ADC-based systems and noise prone devices in order to detect noise and leads to further signal improvement.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122092114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras 一种用于下一代数码相机JPEG2000中EBCOT第一层编码器的混合双核可重构处理器

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706250

Xin Zhao, A. Erdogan, T. Arslan

{"title":"A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras","authors":"Xin Zhao, A. Erdogan, T. Arslan","doi":"10.1109/DASIP.2010.5706250","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706250","url":null,"abstract":"In this paper, we present a JPEG2000 EBCOT tier-1 encoder based on a hybrid dual-core processor composed of a coarse-grained Dynamically Reconfigurable Processor (DRP) and an ARM core targeting next generation of cameras. The complete EBCOT tier-1 encoder is partitioned into two tasks and mapped onto the two cores respectively according to different potentials of the two processors. A Partial Parallel Architecture (PPA) for the Context Modeling (CM) is employed which can be easily tailored for DRP implementation for higher performance. The Arithmetic Encoder (AE) has been optimized as well, with a shared Dual-Port RAM (DPRAM) acting as the communication intermediate between the two cores. For the entire application, the two tasks can be pipelined via the global DPRAM for better performance. Simulation results show that the resulting architecture provides throughput reaching up to 40fps for a 256×256 8-bit grayscale standard Lena test image and shows its advantage compared with some DSP&VLIW applications. In addition, this hybrid processor also shows its high potential for implementing the complete JPEG2000 encoder on it targeting next generation of camera applications.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125306629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1