2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献

An in-memory monitoring database for self adaptive MP2SoCs 用于自适应mp2soc的内存监控数据库

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-26 DOI: 10.1109/DASIP.2010.5706252

Etienne Faure, G. M. Almeida, M. Benabdenbi, P. Benoit, F. Clermidy, F. Pêcheux, G. Sassatelli, L. Torres

引用次数: 2

A new single-error correction scheme based on self-diagnosis residue number arithmetic 一种新的基于自诊断剩余数算法的单误差校正方案

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-26 DOI: 10.1109/DASIP.2010.5706242

Yangyang Tang, E. Boutillon, C. Jégo, M. Jézéquel

引用次数: 18

Physical layer study in a goal of robustness and energy efficiency for wireless sensor networks 以鲁棒性和能量效率为目标的无线传感器网络物理层研究

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-26 DOI: 10.1109/DASIP.2010.5706267

D. Dessales, A. Poussard, R. Vauzelle, N. Richard, F. Gaudaire, C. Martinsons

引用次数: 6

Generation of static tables in embedded memory with dense scheduling 在密集调度的嵌入式内存中生成静态表

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-26 DOI: 10.1109/DASIP.2010.5706253

Benoît Miramond, L. Cucu-Grosjean

引用次数: 4

Dual-core reconfigurable demosaicing engine for next generation of portable camera systems 下一代便携式相机系统的双核可重构去马赛克引擎

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706278

Xin Zhao, Y. Yi, A. Erdogan, T. Arslan

引用次数: 3

Characterization of capture actions in video sequences 视频序列中捕获动作的表征

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706270

Ana Pinzari, M. Shawky

引用次数: 1

Energy modeling of the virtual memory subsystem for real-time embedded systems 实时嵌入式系统虚拟内存子系统的能量建模

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706244

Mickael Lanoe, E. Senn

引用次数: 1

RVC: A multi-decoder CAL Composer tool 一个多解码器CAL Composer工具

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706258

F. Palumbo, D. Pani, Emanuele Manca, L. Raffo, M. Mattavelli, Ghislain Roquier

{"title":"RVC: A multi-decoder CAL Composer tool","authors":"F. Palumbo, D. Pani, Emanuele Manca, L. Raffo, M. Mattavelli, Ghislain Roquier","doi":"10.1109/DASIP.2010.5706258","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706258","url":null,"abstract":"The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of components. The word “reconfigurable” evokes run-time instantiation of different decoders starting from an on-the-fly analysis of the input bitstream. In this paper we move a first step towards the definition of systematic procedures that, based on the MPEG RVC specification formalism, are able to produce multi-decoder platforms, capable of fast switching between different configurations. Looking at the similarities between the decoding algorithms to implement, the papers describes an automatic tool for their composition into a single configurable multi-decoder built of all the required modules, and able to reuse the shared components so as to reduce the overall footprint (either from a hardware or software perspective). The proposed approach, implemented in C++ leveraging on Flex and Bison code generation tools, typically exploited in the compilers front-end, demonstrates to be successful in the composition of two different decoders MPEG-4 Part 2 (SP): serial and parallel.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms 一种精确比较同质多核DSP平台处理器核心架构的方法

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706275

Bertrand Rousseau, P. Manet, Igor Loiselle, J. Legat, H. Vandierendonck

{"title":"A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms","authors":"Bertrand Rousseau, P. Manet, Igor Loiselle, J. Legat, H. Vandierendonck","doi":"10.1109/DASIP.2010.5706275","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706275","url":null,"abstract":"The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128940074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms 面向多核异构平台的RVC编解码器规范的高层次设计空间探索

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706264

Christophe Lucarz, Ghislain Roquier, M. Mattavelli

{"title":"High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms","authors":"Christophe Lucarz, Ghislain Roquier, M. Mattavelli","doi":"10.1109/DASIP.2010.5706264","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706264","url":null,"abstract":"Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++). As we are entering in the multicore era, sequential programs are no longer the most appropriate way to specify algorithms targeted to run on several processing units. The new ISO/MPEG Reconfigurable Video Coding (RVC) standard is proposing a new paradigm for specifying and designing complex signal processing systems. The RVC standard enables specifying new codecs by assembling blocks, or so called Functional Units (FUs) from a standard Video Tool Library (VTL). Flexibility, reusability, and modularity are the key features of RVC. This new way of specifying algorithms clearly simplifies the task of designing future video coding applications by allowing software and hardware reuse across multiple video coding standards. Specifications are provided in the form of an actor and dataflow-based language called CAL. Although the RVC standard does not imply any specific implementation design flow, it is an appropriate starting point for targeting multiple processing units platforms. This paper describes a new model-driven design flow which considers both algorithm and architecture to map RVC codec specifications onto heterogeneous and multi-core systems.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130535790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22