2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献_第2页

A high-level language for programming a NoC-based Dynamic Reconfiguration Infrastructure 一种用于编程基于noc的动态重构基础结构的高级语言

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706239

W. Vanderbauwhede, S. Nabi

引用次数: 0

Runtime adaptive allocation of dynamically mixed tasks on a heterogeneous MPSoC platform 异构MPSoC平台上动态混合任务的运行时自适应分配

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706243

Jia Huang, A. Raabe, C. Buckl, A. Knoll

引用次数: 4

Exploration platform of embedded simd architecture for autonomous retinas 自主视网膜嵌入式simd架构探索平台

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706277

S. Chevobbe, Suresh Pajaniradja, L. Letellier

引用次数: 2

Task placement for dynamic and partial reconfigurable architecture 动态和部分可重构体系结构的任务放置

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706269

Antoine Eiche, D. Chillet, S. Pillement, O. Sentieys

{"title":"Task placement for dynamic and partial reconfigurable architecture","authors":"Antoine Eiche, D. Chillet, S. Pillement, O. Sentieys","doi":"10.1109/DASIP.2010.5706269","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706269","url":null,"abstract":"Managing tasks and resources of reconfigurable system-on-chip is a complex problem which needs specific operating system (OS) functionalities. One of the most important is the task placement which must be done on-line when the application requires flexibility. To ensure an efficient task placement within the reconfigurable resource, OS services must consider the heterogeneity of the reconfigurable resource. While most publications model the reconfigurable resource as homogeneous area, modern reconfigurable circuits are clearly heterogeneous, i.e. there are based on rectangular grid containing logic blocks but also other blocks such as memories, digital signal processing blocks or hard processor cores. In this paper, we tackle the problem of task placement within a reconfigurable resource and we consider a heterogeneous reconfigurable area. Our solution is based on a neural network structure specifically designed to optimize the task placement problem. Our proposition is based on the knowledge of task instantiations within the reconfigurable resource. Compared with other methods, our proposal provides better results in terms of task rejection.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131831706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

GPU architecture evaluation for multispectral and hyperspectral image analysis 多光谱和高光谱图像分析的GPU架构评估

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706255

V. Fresse, D. Houzet, C. Gravier

引用次数: 23

Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture 基于运行时可重构操作员的多媒体体系结构的调度、绑定和路由系统

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706261

E. Raffin, C. Wolinski, François Charot, K. Kuchcinski, Stéphane Guyetant, S. Chevobbe, E. Casseau

引用次数: 29

An in-band reconfigurable network node based on a heterogeneous platform 基于异构平台的带内可重构网络节点

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706240

Erik Markert, Enrico Billich, Claudia Tischendorf, U. Proß, Thilo Leibelt, U. Heinkel, Joachim Knäblein, Axel Schneider

引用次数: 1

A wavelet-based demosaicking algorithm for embedded applications 一种基于小波的嵌入式去马赛克算法

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706251

Sébastien Courroux, Stéphane Guyetant, S. Chevobbe, M. Paindavoine

引用次数: 5

Camera-based system for tracking and position estimation of humans 基于摄像机的人体跟踪和位置估计系统

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706247

R. Hartmann, Fadi Al Machot, Philipp Mahr, C. Bobda

引用次数: 13

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation 设计动态可重构soc:从UML MARTE模型到自动代码生成

2010 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2010-10-01 DOI: 10.1109/DASIP.2010.5706248

I. Quadri, S. Meftali, J. Dekeyser

{"title":"Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation","authors":"I. Quadri, S. Meftali, J. Dekeyser","doi":"10.1109/DASIP.2010.5706248","DOIUrl":"https://doi.org/10.1109/DASIP.2010.5706248","url":null,"abstract":"Due to continuous hardware/software evolution related to Systems-on-Chip (SoC) and the addition of features such as Partial Dynamic Reconfiguration, the complexity of SoC design and development has escalated exponentially. This has resulted in increased time to market and development costs. Without the usage of effective design tools and methodologies, large complex SoCs are becoming increasingly difficult to manage, resulting in a productivity gap. The design space, representing all technical decisions that need to be elaborated by the SoC design team is therefore, becoming immense and difficult to explore. Similarly, manipulation of these systems at low implementation levels such as Register Transfer Level (RTL) can be hindered by human interventions and the subsequent errors. This paper presents a novel design methodology that decreases the design complexity by raising the design abstraction levels. It makes use of Model-Driven Engineering and the UML MARTE profile to move from high level UML models to automatic code generation, for implementing dynamically reconfigurable SoCs.","PeriodicalId":158162,"journal":{"name":"2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15