2017 International Symposium on Rapid System Prototyping (RSP)最新文献_第2页

Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates 用c++模板构造可配置加速器的快速和周期精确模拟器

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130324

Michael Witterauf, Frank Hannig, J. Teich

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引用次数: 0

Binary Synthesis Implementing External Interrupt Handler as Independent Module 作为独立模块实现外部中断处理程序的二进制合成

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130317

Naoya Ito, Yuuki Oosako, N. Ishiura, H. Kanbara, H. Tomiyama

引用次数: 3

GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Learning 用于片上学习的分类受限玻尔兹曼机器硬件

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3138856

Wooseok Yi, Junki Park, Jae-Joon Kim

引用次数: 1

Speculative Execution in Distributed Controllers for High-Level Synthesis 面向高级综合的分布式控制器的推测执行

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130319

Miho Shimizu, N. Ishiura, Sayuri Ota, W. Nakano

引用次数: 1

Prototyping Dynamic Task Migration on Heterogeneous Reconfigurable Systems 异构可重构系统的动态任务迁移原型

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130316

Arief Wicaksana, A. Bourge, O. Muller, A. Sasongko, F. Rousseau

{"title":"Prototyping Dynamic Task Migration on Heterogeneous Reconfigurable Systems","authors":"Arief Wicaksana, A. Bourge, O. Muller, A. Sasongko, F. Rousseau","doi":"10.1145/3130265.3130316","DOIUrl":"https://doi.org/10.1145/3130265.3130316","url":null,"abstract":"Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123988900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3