2017 International Symposium on Rapid System Prototyping (RSP)最新文献

Rapid Prototyping of IoT Applications with Esperanto Compiler 物联网应用的快速原型与世界语编译器

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3138857

Gyeongmin Lee, Seonyeong Heo, Bongjun Kim, Jong Kim, Hanjun Kim

{"title":"Rapid Prototyping of IoT Applications with Esperanto Compiler","authors":"Gyeongmin Lee, Seonyeong Heo, Bongjun Kim, Jong Kim, Hanjun Kim","doi":"10.1145/3130265.3138857","DOIUrl":"https://doi.org/10.1145/3130265.3138857","url":null,"abstract":"Integrating various networked devices, the Internet of Things (IoT) enables various new services like home automation, making its market larger and more competitive. Although rapid development of an IoT application is crucial to keep up with the highly competitive IoT market, developing an IoT application is challenging for programmers because the programmers should integrate multiple programmable devices and heterogeneous third-party devices. Some IoT frameworks integrate programming environments of multiple devices, but they either require device-specific implementation for third-party devices without any device abstraction, or abstract all the devices to the standard interfaces requiring unnecessary abstraction of programmable devices. This work introduces the Esperanto framework that integrates IoT devices with selective abstraction, allowing rapid prototyping of an IoT application. Exploiting the correspondence between an object and a thing in the object oriented programming (OOP) model, the Esperanto framework allows programmers to write only one OOP program instead of multiple programs for each device, and to manipulate third-party devices with their common ancestor classes. Compared to an existing approach on the integrated IoT programming, Esperanto requires 33.3% fewer lines of code to implement 5 IoT services, and reduces their response time by 44.8% on average. Moreover, with an empirical study, this work shows that the Esperanto framework reduces the development time by 52.7%.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123075021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An Analysis of Random Cache Effects on Real-Time Multi-Core Scheduling Algorithms 随机缓存对实时多核调度算法的影响分析

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130320

Imane Hafnaoui, Chao Chen, Rabeh Ayari, G. Nicolescu, G. Beltrame

引用次数: 1

Software Platform Dedicated for In-Memory Computing Circuit Evaluation 内存计算电路评估专用软件平台

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130322

Maha Kooli, H. Charles, C. Touzet, B. Giraud, J. Noël

引用次数: 5

One-Instruction Set Computer-Based Multicore Processors for Energy-Efficient Streaming Data Processing 高效流数据处理的单指令集计算机多核处理器

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130318

Minato Yokota, Kaoru Saso, Yuko Hara-Azumi

{"title":"One-Instruction Set Computer-Based Multicore Processors for Energy-Efficient Streaming Data Processing","authors":"Minato Yokota, Kaoru Saso, Yuko Hara-Azumi","doi":"10.1145/3130265.3130318","DOIUrl":"https://doi.org/10.1145/3130265.3130318","url":null,"abstract":"For architecture designs, flexibility of application-dependent optimization for better performance and energy-efficiency and productivity enhanced by application-independent versatility and reusability are both crucial but contradicting issues. In the IoT era, due to a more stringent energy constraint and more application diversity, such issues are becoming more difficult to satisfy. Even recent embedded processors prioritize the design-productivity over flexibility, leading to a lot of energy waste in unused resources for some applications. This paper proposes novel multicore processors to address the above two issues. Our processors are composed of application-independent tiny cores and application-dependent optimizable inter-core communications, which efficiently execute applications on a large amount of streaming data, in a pipeline manner. In this work, we utilize one of the simplest RISC processors, One-Instruction Set Computer (OISC), as a core. Our evaluation demonstrates that our processors outperform an existing RISC processor in terms of performance (throughput) and energy-efficiency, while having sufficient scalability, for two different types of applications.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126383837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

PoliCym: Rapid Prototyping of Resource Management Policies for HMPs PoliCym: hmp资源管理策略的快速原型

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130321

T. Mück, Bryan Donyanavard, N. Dutt

{"title":"PoliCym: Rapid Prototyping of Resource Management Policies for HMPs","authors":"T. Mück, Bryan Donyanavard, N. Dutt","doi":"10.1145/3130265.3130321","DOIUrl":"https://doi.org/10.1145/3130265.3130321","url":null,"abstract":"Heterogeneous Multiprocessors (HMPs) are becoming pervasive in current modern embedded platforms (e.g. mobile devices). These platforms often provide better power-performance tradeoffs than their homogeneous predecessors; however, novel and intelligent resource management policies are required to manage the added complexity of heterogeneous platforms and exploit their power-performance benefits. In this paper we propose PoliCym, a framework for the prototyping, validating, and deploying resource management policies for heterogeneous platforms. PoliCym provides two main benefits to resource management policy developers and to the research community: 1) a trace-based offline simulator allows policies to be quickly prototyped, debugged, and validated on top of arbitrary platform configurations; and 2) a light-weight sensing-actuation interface allows the same policies to be efficiently deployed on top of Linux-based systems without the need for implementation changes or additional development cycles. We evaluate our light-weight interface in terms of overhead and validate the PoliCym offline simulator for an ARM big.LITTLE based HMP platform running Linux.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Time Synchronization Services for Low-Cost Fog Computing Applications 低成本雾计算应用的时间同步服务

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130325

P. Völgyesi, A. Dubey, T. Krentz, I. Madari, Mary Metelko, G. Karsai

引用次数: 21

Executable Dataflow Benchmark Generation Technique for Multi-Core Embedded Systems 多核嵌入式系统可执行数据流基准生成技术

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130323

Jeonggyu Jang, Hoeseok Yang

{"title":"Executable Dataflow Benchmark Generation Technique for Multi-Core Embedded Systems","authors":"Jeonggyu Jang, Hoeseok Yang","doi":"10.1145/3130265.3130323","DOIUrl":"https://doi.org/10.1145/3130265.3130323","url":null,"abstract":"As the complexity of multi-core embedded systems continuously grows, the optimization and verification of such systems become non-trivial. Thus, it is important to secure a set of benchmarks of reasonable complexity to validate the design of multi-core embedded systems. Dataflow model has long been considered as a suitable model-of-computation for specifying the behavior of embedded systems. In this paper, we proposes a dataflow benchmark generation technique for multi-core embedded systems, leveraging two existing tools: a random dataflow topology generator and a random C code generator. In the proposed technique, as a preparatory step, a C code database is established by means of a random C code generation tool Then, a random dataflow graph, with execution time information annotated to each node, is generated by an existing tool For each node in the generated graph, a number of randomly generated C code segments are properly chosen and accommodated in a single function as per the given execution time information. In doing so, a set of linear equations are derived and solved. Subsequently, using existing model-based embedded system design frameworks, we automatically generate an executable benchmark for the entire dataflow graph. Further, in order to enhance the accuracy of the generated code, a simple calibration technique is applied after the generation and test runs. It is shown that the generated codes assure the diversity and complexity as embedded software benchmark for multi-core embedded systems.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129020492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient and Robust Middleware Prototyping for Smart Mobile Computing 智能移动计算的节能和健壮中间件原型

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3138855

Saideep Tiku, S. Pasricha

引用次数: 4

Simulation-Based Circuit-Activity Estimation for FPGAs Containing Hard Blocks 基于仿真的包含硬块的 FPGA 电路活动估计

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3130326

Sean Seeley, Vidya Sankaranaryanan, Zack Deveau, Panagiotis Patros, K. Kent

引用次数: 1

The Extendable Translating Instruction Set Simulator (ETISS) Interlinked with an MDA Framework for Fast RISC Prototyping 基于MDA框架的可扩展翻译指令集模拟器(ETISS)的快速RISC原型设计

2017 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2017-10-19 DOI: 10.1145/3130265.3138858

Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, W. Ecker, Marc Greim, Ulf Schlichtmann

{"title":"The Extendable Translating Instruction Set Simulator (ETISS) Interlinked with an MDA Framework for Fast RISC Prototyping","authors":"Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, W. Ecker, Marc Greim, Ulf Schlichtmann","doi":"10.1145/3130265.3138858","DOIUrl":"https://doi.org/10.1145/3130265.3138858","url":null,"abstract":"This paper describes the Extendable Translating Instruction Set Simulator (ETISS). In addition to binary translation, ETISS features a plugin mechanism that allows to quickly include new functionality into the translation stage, the simulation loop, during accesses to the memory or whenever an interrupt is received. ETISS targets to become an advanced industrial-strength ISS with special focus on virtual prototypes (VPs) written in SystemC/TLM. In this paper, we will show examples of ETISS Plugins, which include tracing tools, SystemC interfaces, closey-coupled peripherals or triggers for fault injection. A major drawback of developing a new binary translator such as ETISS is its lack of support for a variety of instruction set architectures (ISAs). At the moment ETISS supports the open-source OpenRISC or 1k and partly RISC-V ISAs. Yet, in order to overcome this problem, we developed a toolchain to generate the binary translation stage for different ISAs following the MDA concept based on meta-modeling and code generation. It is planned to make ETISS available as an open-source tool to the research community.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124773076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19