异构可重构系统的动态任务迁移原型

Arief Wicaksana, A. Bourge, O. Muller, A. Sasongko, F. Rousseau
{"title":"异构可重构系统的动态任务迁移原型","authors":"Arief Wicaksana, A. Bourge, O. Muller, A. Sasongko, F. Rousseau","doi":"10.1145/3130265.3130316","DOIUrl":null,"url":null,"abstract":"Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.","PeriodicalId":157455,"journal":{"name":"2017 International Symposium on Rapid System Prototyping (RSP)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Prototyping Dynamic Task Migration on Heterogeneous Reconfigurable Systems\",\"authors\":\"Arief Wicaksana, A. Bourge, O. Muller, A. Sasongko, F. Rousseau\",\"doi\":\"10.1145/3130265.3130316\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.\",\"PeriodicalId\":157455,\"journal\":{\"name\":\"2017 International Symposium on Rapid System Prototyping (RSP)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Symposium on Rapid System Prototyping (RSP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/3130265.3130316\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Symposium on Rapid System Prototyping (RSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3130265.3130316","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

可重构器件,如fpga,在计算方面具有优异的性能和高效率。由于其容量的提高和更高效的架构,在可重构系统中使用fpga作为协处理器的兴趣越来越大。然而,fpga仍然缺乏对动态调度的支持,例如在一个系统中管理多个任务或用户。除非可重构系统支持动态任务迁移,否则不可能执行运行时任务重新定位或负载分配。这种能力需要在可重构体系结构中实现配置和上下文管理的自动化,这在现有的解决方案中是不可用的。在本文中,我们提出了一个在异构fpga之间进行动态任务迁移的原型框架。在一个FPGA上运行的任务可以在另一个不同架构的FPGA上暂停和恢复。由于任务提供的特定于任务的提取机制,FPGA寄存器和内存值的提取和恢复是可能的。该框架利用与FPGA紧密耦合的高性能嵌入式处理器来自动管理配置和上下文。它在实现中使用两种流行的异构可重构系统,Xilinx Zynq ZC706和Altera Arria V SoC。使用图形和非图形基准应用程序执行了测试,并给出了性能结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Prototyping Dynamic Task Migration on Heterogeneous Reconfigurable Systems
Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.
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