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Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)最新文献

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Effect of the selection MOS transistor polarization voltage during a write and an erase operation of an EEPROM memory cell 在EEPROM存储器单元的写入和擦除操作期间选择MOS晶体管极化电压的影响
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825590
W. Benzerti, R. Bouchakour, J. Mirabel, P. Boivin
{"title":"Effect of the selection MOS transistor polarization voltage during a write and an erase operation of an EEPROM memory cell","authors":"W. Benzerti, R. Bouchakour, J. Mirabel, P. Boivin","doi":"10.1109/ICM.1998.825590","DOIUrl":"https://doi.org/10.1109/ICM.1998.825590","url":null,"abstract":"The use of EEPROM memory cells has covered in the last years a wide range of applications. These are of analog and mixed type. In order to improve the good behavior and the exploration of new applications, the development of an efficient and compact EEPROM memory cell model seems to be a necessity. Previous studies usually focused on the floating gate MOS transistor performance without knowledge of the selection MOS transistor effect during real functioning of a cell in an EEPROM matrix. This paper is a first approach to the evaluation of the select gate voltage variations effect on memory cell performance.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129367920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High performance balanced current controlled amplifiers 高性能平衡电流控制放大器
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825595
H. Zouaoui-Abouda, A. Fabre
{"title":"High performance balanced current controlled amplifiers","authors":"H. Zouaoui-Abouda, A. Fabre","doi":"10.1109/ICM.1998.825595","DOIUrl":"https://doi.org/10.1109/ICM.1998.825595","url":null,"abstract":"High performance balanced current controlled voltage-mode amplifiers are presented. They are constituted of four class AB controlled conveyors and do not require any external passive component. They are easily tunable from the bias currents which give to them a good versatility. These fully differential amplifiers provide wide bandwidth, low harmonic distortion and very low output offset voltage.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low power CMOS digital design 低功耗CMOS数字设计
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825543
Alain Guyot, S. Abou-Samra
{"title":"Low power CMOS digital design","authors":"Alain Guyot, S. Abou-Samra","doi":"10.1109/ICM.1998.825543","DOIUrl":"https://doi.org/10.1109/ICM.1998.825543","url":null,"abstract":"This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to statistically measure the average number of transitions (or activity). In a second part, the paper will show the incidence of scaling down the transistors on power dissipation. The third part will address the question: what is performance. Next, the fourth part will discuss complexity versus dissipation and finally glitch filtering.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134299362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
High performance integrated CMOS frequency-to-voltage converter 高性能集成CMOS频率-电压转换器
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825568
A. Djemouai, M. Sawan, M. Slamani
{"title":"High performance integrated CMOS frequency-to-voltage converter","authors":"A. Djemouai, M. Sawan, M. Slamani","doi":"10.1109/ICM.1998.825568","DOIUrl":"https://doi.org/10.1109/ICM.1998.825568","url":null,"abstract":"In this paper we present a new high performance frequency-to-voltage converter (FVC) dedicated for integrated CMOS mixed-signal (analog/digital) applications. The circuit is very fast and requires a very small silicon area for integration. The output voltage generated by this FVC does not present any AC ripples and is proportional to the period of a square wave form input signal. The time response of this FVC is very small and is approximately equal to eight cycles of the input signal within a precision of 0.4%. The circuit can operate theoretically up to 100 MHz and its operating frequency range can easily be changed.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A low-voltage current-controlled oscillator with low supply dependency 具有低电源依赖性的低压电流控制振荡器
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825619
A. M. Sodagar, S. M. Fakhraie, K. smith
{"title":"A low-voltage current-controlled oscillator with low supply dependency","authors":"A. M. Sodagar, S. M. Fakhraie, K. smith","doi":"10.1109/ICM.1998.825619","DOIUrl":"https://doi.org/10.1109/ICM.1998.825619","url":null,"abstract":"A new current-controlled oscillator (CCO) is presented which is suitable for use in low-voltage and low-power designs. These features, and the low supply dependence of this CCO all stem from using a regenerative mechanism in its primitive delay cells. The circuit is designed and simulated in a 0.8 /spl mu/m BiCMOS technology.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A static method for system performance estimation 一种静态的系统性能估计方法
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825581
N. Chabini, I. Bennour, E. Aboulhamid, Y. Savaria
{"title":"A static method for system performance estimation","authors":"N. Chabini, I. Bennour, E. Aboulhamid, Y. Savaria","doi":"10.1109/ICM.1998.825581","DOIUrl":"https://doi.org/10.1109/ICM.1998.825581","url":null,"abstract":"Performance estimation techniques and tools help designers to quickly determine appropriate computer architectures and programmers to optimize implementations for specific applications. In this paper, we present a method for system performance estimation. Based on this method we developed a tool which accepts a generic architecture and applications written in the C language. The tool is integrated with a retargetable C compiler which allows a better estimation as illustrated by the experimental results. We have used this tool to estimate the performance of the PULSE-V1 SIMD parallel system.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127608061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System testability evaluation with STA 基于STA的系统可测试性评估
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825573
W. Maroufi, M. Marzouki
{"title":"System testability evaluation with STA","authors":"W. Maroufi, M. Marzouki","doi":"10.1109/ICM.1998.825573","DOIUrl":"https://doi.org/10.1109/ICM.1998.825573","url":null,"abstract":"This paper presents a Computer Aided Testability tool named STA (System Testability Assistant), aimed at proposing a testability strategy for systems as early as possible in the design process. Given a system description, STA first compiles it in order to create system, boards, and circuits objects, and then proceeds bottom-up, from the circuit to the system, in order to evaluate the actual testability of the whole system, recommend a testability strategy and testability features inclusion in some modules, and provides support for including these testability features in the system by calling external generators or synthesis for testability tools.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new structure of switched current integrator 一种开关电流积分器的新结构
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825598
M. Loulou, P. Marchegay, H. Traff, N. Masmoudi, L. Kamoun
{"title":"A new structure of switched current integrator","authors":"M. Loulou, P. Marchegay, H. Traff, N. Masmoudi, L. Kamoun","doi":"10.1109/ICM.1998.825598","DOIUrl":"https://doi.org/10.1109/ICM.1998.825598","url":null,"abstract":"This paper propose a new switched current integrator, using a fully differential bilinear structure with a current mode common mode rejection. This proposed structure offer a gain in sampling speed equal to the double of the clock frequency used. It also offer considerable gain in power consumption and area occupation.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128962570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low energy implantation and transient enhanced diffusion: a reliable approach to secondary defect profile measurements 低能量注入和瞬态增强扩散:二次缺陷轮廓测量的可靠方法
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825583
L. Soliman, M. Benzohra, M. Masmoudi, K. Ketata, F. Olivié, A. Martinez, M. Ketata
{"title":"Low energy implantation and transient enhanced diffusion: a reliable approach to secondary defect profile measurements","authors":"L. Soliman, M. Benzohra, M. Masmoudi, K. Ketata, F. Olivié, A. Martinez, M. Ketata","doi":"10.1109/ICM.1998.825583","DOIUrl":"https://doi.org/10.1109/ICM.1998.825583","url":null,"abstract":"It is well known that low energy implantation is the most promising option for ultra shallow junction formation in the next generation of silicon BiCMOS technology. Among the dopants that have to be implanted, boron is the most problematic because of its low stopping power and its tendency to undergo transient enhanced diffusion and clustering during thermal activation. This paper reports an experimental contribution with the help of secondary defect profiles to our understanding of low energy B implants in crystalline silicon. Shallow p/sup +/n junctions were formed by low energy B implantation-10/sup 15/ cm/sup -2/ at 3 keV-into a n-type monocrystalline silicon preamorphized with germanium. Rapid thermal annealing for 15 s at 950/spl deg/C was then used for dopant electrical activation and implantation damage removal. A reliable approach using the secondary defect profiles induced by this process, measured with isothermal transient capacitance in association with deep level transient spectroscopy is proposed. A relatively high concentration of B-related electrically active defects have been obtained up to 3.5 /spl mu/m into the crystalline silicon bulk.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-level testability evaluation of TASS synthesized systems TASS综合系统的高水平可测试性评价
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825572
M. Jamoussi, S. Amellal, B. Kaminska
{"title":"High-level testability evaluation of TASS synthesized systems","authors":"M. Jamoussi, S. Amellal, B. Kaminska","doi":"10.1109/ICM.1998.825572","DOIUrl":"https://doi.org/10.1109/ICM.1998.825572","url":null,"abstract":"In this paper, a new synthesis system, called TASS (TAbu search Synthesis System), is presented. It enables a Register-Transfer Level (RTL) implementation from a functional VHDL description. Furthermore, an emphasis on how testability evaluation is incorporated in the synthesis process in order to generate not only optimized designs, with regard to area and delay, but also fully and easily testable architectures. Such testability evaluation is performed at the RTL using developed testability measures. These measures are benchmarked on high-level synthesized examples and the testability analysis of the generated designs is performed using the test compiler tool of Synopsys.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126206040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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