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Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)最新文献

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Simple multifunction filter realizations with current conveyors 简单的多功能过滤器实现与当前的输送机
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825600
O. Cicekoglu, S.E. Ak
{"title":"Simple multifunction filter realizations with current conveyors","authors":"O. Cicekoglu, S.E. Ak","doi":"10.1109/ICM.1998.825600","DOIUrl":"https://doi.org/10.1109/ICM.1998.825600","url":null,"abstract":"A new current conveyor based filter topology with two different realisation possibilities using only positive type second generation current conveyors and only grounded passive components is presented. For both possibilities no element matching conditions are imposed. The filters permit orthogonal adjustment of quality factor Q and resonant angular frequency /spl omega//sub 0/. The circuits exhibit high input impedance thus enable easy cascadability. The passive sensitivities are shown to be low. The functionality of one of the circuits is tested on a filter design example by experiment.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129450956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
YAGLE, a second generation functional abstractor for CMOS VLSI circuits YAGLE, CMOS VLSI电路的第二代功能抽象器
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825615
A. Lester, Pirouz Bazargan-Sabet, A. Greiner
{"title":"YAGLE, a second generation functional abstractor for CMOS VLSI circuits","authors":"A. Lester, Pirouz Bazargan-Sabet, A. Greiner","doi":"10.1109/ICM.1998.825615","DOIUrl":"https://doi.org/10.1109/ICM.1998.825615","url":null,"abstract":"This paper presents a new functional abstraction tool for CMOS VLSI. The tool uses a procedure called circuit disassembly in order to extract an oriented gate netlist from a transistor netlist. Logic equations are then generated for these extracted gates in order to produce a VHDL data-flow description for a circuit. This tool combines an advanced functional analysis technique with subgraph isomorphism algorithms in order to handle the widest possible number of circuit styles with a minimum of user intervention.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121850088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Fabrication of photoresist microlens arrays 光刻胶微透镜阵列的制备
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825565
H. Alhokail
{"title":"Fabrication of photoresist microlens arrays","authors":"H. Alhokail","doi":"10.1109/ICM.1998.825565","DOIUrl":"https://doi.org/10.1109/ICM.1998.825565","url":null,"abstract":"Microlens arrays are used in optical systems to direct light from sources to detectors. In this paper the method of melted photoresist is used to fabricate an array of microlenses. The experimental results as well as the main processing factors that affect the uniformity of such lenses are presented.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125288841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of neural nets for character recognition 用于字符识别的神经网络设计
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825620
H. El-Bakry, M. Abo-Elsoud
{"title":"Design of neural nets for character recognition","authors":"H. El-Bakry, M. Abo-Elsoud","doi":"10.1109/ICM.1998.825620","DOIUrl":"https://doi.org/10.1109/ICM.1998.825620","url":null,"abstract":"In this paper, the possibility of using Artificial Neural Networks (ANNs) in the field of character recognition is discussed. Our study is undertaken on theoretical and practical investigations of two feedforward models (the Prototype Multilayer Perceptron (MLP) and the Fully Connected model) by using the backpropagation training algorithm. We introduce a fully connected network of three layers in order to make a classification between two characters T and C without being affected by shift in position, rotation, or scaling. A complete analog implementation is presented by using D-MOS transistors acting as synaptic weights and bipolar transistors to represent the nonlinear sigmoid function. Simulation results for fully connected networks are compared with those of traditional techniques (prototype MLP model) in order to recognize more characters.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Early branch prediction circuit for high performance digital signal processors 高性能数字信号处理器早期支路预测电路
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825577
A. Farooqui, V. Oklobdzija
{"title":"Early branch prediction circuit for high performance digital signal processors","authors":"A. Farooqui, V. Oklobdzija","doi":"10.1109/ICM.1998.825577","DOIUrl":"https://doi.org/10.1109/ICM.1998.825577","url":null,"abstract":"In this paper, design and VLSI implementation of an Early Branch Prediction (EBP) circuit, based on a variation of Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2[log n/2]+1), and high modularity. This design out performs all the EBP designs presented so far. For 64 bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2 /spl mu/ technology under typical conditions. Simulation and layout results for 0.2 /spl mu/ CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New design using a VHDL description for DCT based circuits 新的设计使用VHDL描述基于DCT的电路
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825575
M.A. BenAyed, L. Dulau, P. Nouel, Y. Berthournieu, N. Masmoudi, P. Kadionik, L. Kamoun
{"title":"New design using a VHDL description for DCT based circuits","authors":"M.A. BenAyed, L. Dulau, P. Nouel, Y. Berthournieu, N. Masmoudi, P. Kadionik, L. Kamoun","doi":"10.1109/ICM.1998.825575","DOIUrl":"https://doi.org/10.1109/ICM.1998.825575","url":null,"abstract":"This paper presents a new method to implement the DCT algorithm for JPEG or MPEG compression using VHDL description in ASIC or FPGA circuits. Discrete Cosine Transform (DCT) is one of the most popular lossy techniques used today in video compression schemes. Several algorithms have been proposed to implement the DCT. Loeffler (1989) has given a new class of 1D-DCT using just 11 multiplications and 29 additions. To implement such an algorithm, one or more multipliers have to be integrated. This requires a high silicon occupation area. Arithmetic distribution is widely used for such algorithms. However, its direct implementation requires an important silicon occupation area due to the ROM size needed. This paper presents a new technique based on the fusion of distributed arithmetic with Loeffler's algorithm to over come the above problems. We present a 1D-DCT design. This circuit has been implemented in Xilinx FPGAs.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"493 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133836767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Programmable current source dedicated to implantable microstimulators 可编程电流源专用于植入式微刺激器
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825569
J.-C. Voghell, M. Sawan, M. Roy, S. Bourret
{"title":"Programmable current source dedicated to implantable microstimulators","authors":"J.-C. Voghell, M. Sawan, M. Roy, S. Bourret","doi":"10.1109/ICM.1998.825569","DOIUrl":"https://doi.org/10.1109/ICM.1998.825569","url":null,"abstract":"In this paper, a survey of programmable current-source architectures based on miniaturized digital-to-analog converters (DAC) is elaborated to propose a new design dedicated to a visual microstimulator. The needed current-source constitutes the electronic interface to tissues. A few samples of this current-source will be integrated in an implantable device which is powered and controlled using an electromagnetic coupling technique. The main objective is to select a design that meets as close as possible criteria related to the implant such as reliability, flexibility, energy efficiency and integration area. Consequently, an adequate current source is proposed which is a 5-bit thermometer-code-based DAC architecture. The resulting circuit is simulated using a 0.35 /spl mu/m CMOS technology from PMC-Sierra available through the Canadian Microelectronics Corporation (CMC).","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131137463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A parallel technique for ATPG using genetic algorithms 基于遗传算法的ATPG并行技术
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825571
M. Sabry, A. Wahba, H. Mahdi
{"title":"A parallel technique for ATPG using genetic algorithms","authors":"M. Sabry, A. Wahba, H. Mahdi","doi":"10.1109/ICM.1998.825571","DOIUrl":"https://doi.org/10.1109/ICM.1998.825571","url":null,"abstract":"This paper presents a new technique for test pattern generation based on a genetic algorithm and parallel processing techniques. This new method offers compact test sets, compared to other methods, that achieve maximum coverage.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131350495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cache coherence protocol verification of a multiprocessor system with shared memory 具有共享内存的多处理器系统的缓存一致性协议验证
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825578
M. Azizi, O. Ait Mohamed, Xiaoyu Song
{"title":"Cache coherence protocol verification of a multiprocessor system with shared memory","authors":"M. Azizi, O. Ait Mohamed, Xiaoyu Song","doi":"10.1109/ICM.1998.825578","DOIUrl":"https://doi.org/10.1109/ICM.1998.825578","url":null,"abstract":"In this paper, we present the verification of a multiprocessor system with shared memory, using VIS tool. This system consists of three processors; each one has its cache and all share the main memory and the bus. Its RTL-level design is described in Verilog-HDL and the properties to be verified, in CTL. Also, we establish the effect of data width upon the reachability analysis. As results, safety and liveness properties are fulfilled by the system design, and a fast increase of reachable state number and BDD (Binary Decision Diagram) size is observed when the data width or the processor number are growing. By using MDG tool, we plan to resolve the negative effect of cache size increase.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116702843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error 使用雷诺阿工具的FPGA实现:用于位时序逻辑(BTL)合成控制器局域网的应用，具有100%的自由误差
Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186) Pub Date : 1998-12-14 DOI: 10.1109/ICM.1998.825560
K. Abouda, J. Ducaud, H. Henry, J. Aucouturier
{"title":"FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error","authors":"K. Abouda, J. Ducaud, H. Henry, J. Aucouturier","doi":"10.1109/ICM.1998.825560","DOIUrl":"https://doi.org/10.1109/ICM.1998.825560","url":null,"abstract":"Logic synthesis using VHDL simplifies considerably logic circuit design. However, when the application requires a few thousand lines of VHDL code, it is very beneficial to use graphic software that can produce the VHDL code. But, it is always necessary to master the VHDL language. In this paper we have studied VHDL generated with three basic processes of the Renoir state machine. An application for designing, synthesizing and implementing a bit timing logic of an ISO normalized controller area network (CAN) is given. It has been tested with 100% free error.","PeriodicalId":156747,"journal":{"name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115368004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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