Effect of the selection MOS transistor polarization voltage during a write and an erase operation of an EEPROM memory cell

The use of EEPROM memory cells has covered in the last years a wide range of applications. These are of analog and mixed type. In order to improve the good behavior and the exploration of new applications, the development of an efficient and compact EEPROM memory cell model seems to be a necessity. Previous studies usually focused on the floating gate MOS transistor performance without knowledge of the selection MOS transistor effect during real functioning of a cell in an EEPROM matrix. This paper is a first approach to the evaluation of the select gate voltage variations effect on memory cell performance.