International Conference on Embedded Software最新文献_第2页

SmartDTM: smart thermal management for smartphones: work-in-progress SmartDTM:智能手机的智能热管理:正在进行中

International Conference on Embedded Software Pub Date : 2017-10-15 DOI: 10.1145/3125503.3125567

Wook Song, Jihong Kim

引用次数: 0

Verifying stability guarantees of control software implementations in the presence of sensor level faults: work-in-progress 在存在传感器级故障的情况下验证控制软件实现的稳定性保证:正在进行的工作

International Conference on Embedded Software Pub Date : 2017-10-15 DOI: 10.1145/3125503.3125569

S. Ghosh, D. Lohar, Dibyendu Das, Soumyajit Dey

引用次数: 0

Integrating low-power IoT devices to a blockchain-based infrastructure: work-in-progress 将低功耗物联网设备集成到基于区块链的基础设施:工作正在进行中

International Conference on Embedded Software Pub Date : 2017-10-15 DOI: 10.1145/3125503.3125628

Kazim Rifat Özyilmaz, A. Yurdakul

引用次数: 60

Multiple shooting, CEGAR-based falsification for hybrid systems 基于cegar的混合系统多重射击伪证

International Conference on Embedded Software Pub Date : 2014-10-12 DOI: 10.1145/2656045.2656061

Aditya Zutshi, Jyotirmoy V. Deshmukh, S. Sankaranarayanan, J. Kapinski

引用次数: 57

Flattening hierarchical scheduling 扁平化分层调度

International Conference on Embedded Software Pub Date : 2012-10-07 DOI: 10.1145/2380356.2380376

A. Lackorzynski, Alexander Warg, M. Völp, Hermann Härtig

引用次数: 63

Assessing the suitability of the NGMP multi-core processor in the space domain 评估NGMP多核处理器在空间领域的适用性

International Conference on Embedded Software Pub Date : 2012-10-07 DOI: 10.1145/2380356.2380389

Mikel Fernández, R. Gioiosa, E. Quiñones, L. Fossati, Marco Zulianello, F. Cazorla

{"title":"Assessing the suitability of the NGMP multi-core processor in the space domain","authors":"Mikel Fernández, R. Gioiosa, E. Quiñones, L. Fossati, Marco Zulianello, F. Cazorla","doi":"10.1145/2380356.2380389","DOIUrl":"https://doi.org/10.1145/2380356.2380389","url":null,"abstract":"Multi-core processors are increasingly being considered as a means to provide the performance required by future safety-critical embedded systems. In this line, Aeroflex Gaisler has developed, in conjunction with the European Space Agency, the NGMP, a quad-core processor to be used in the future space missions of the Agency. Unfortunately, the use of multi-core processors in industrial domains is not straightforward since it poses various challenges on the timing behavior of the system. This is mainly due to the interferences tasks suffer when accessing hardware shared resources and which can affect their WCET. Although the effect of inter-task interferences in multi-core shared resources on real-time applications has received attention from academia, most of the solutions proposed require hardware changes. The lack of quantitative studies of the slowdown on applications' performance caused by inter-task interferences on real COTS multi-core processors, limit their use by industry.\u0000 As a first step to understand the effect of inter-task interference in real COTS processors, this paper evaluates the timing predictability properties of the NGMP. In particular, we measure the maximum variation on tasks' execution time due to inter-task interferences accessing NGMP's shared hardware resources. To that end, we use a set of specialized micro-benchmarks designed to stress specific processor shared resources. The results of this can be useful for developing interference-aware WCET estimation methodologies and scheduling algorithms for real-time applications running on embedded multi-core processors.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128894208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 67

Compositional temporal analysis model for incremental hard real-time system design 增量式硬实时系统设计的组合时间分析模型

International Conference on Embedded Software Pub Date : 2012-10-07 DOI: 10.1145/2380356.2380390

J. Hausmans, Stefan J. Geuns, M. Wiggers, M. Bekooij

{"title":"Compositional temporal analysis model for incremental hard real-time system design","authors":"J. Hausmans, Stefan J. Geuns, M. Wiggers, M. Bekooij","doi":"10.1145/2380356.2380390","DOIUrl":"https://doi.org/10.1145/2380356.2380390","url":null,"abstract":"The incremental design and analysis of parallel hard real-time stream processing applications is hampered by the lack of an intuitive compositional temporal analysis model that supports arbitrary cyclic dependencies between tasks.\u0000 This paper introduces a temporal analysis model for hard real-time systems, called the Compositional Temporal Analysis (CTA) model, in which arbitrary cyclic dependencies can be specified. The CTA model also supports hierarchical composition and incremental design of timed components. The internals of a component in the CTA model can be hidden without changing the temporal properties of the component. Furthermore, the composition operation in the CTA model is associative, which enables composing components in an arbitrary order. Besides all these properties, also latency constraints and periodic sources and sinks can be specified and analyzed.\u0000 We also show in this paper that for the CTA model efficient algorithms exist for buffer sizing, verifying consistency of compositions and to compute the temporal properties of compositions.\u0000 The CTA model can be used as an abstraction of timed dataflow models. The CTA model uses components with transfer rates per port, in contrast to dataflow models that use actors with firing rules. Unlike dataflow models, the CTA model is not executable.\u0000 An audio echo cancellation application is used to illustrate the applicability of the CTA model for a stream processing application with throughput and latency constraints, and to illustrate incremental design.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128372297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Operating system support for redundant multithreading 操作系统支持冗余多线程

International Conference on Embedded Software Pub Date : 2012-10-07 DOI: 10.1145/2380356.2380375

Björn Döbel

引用次数: 64

Towards network-on-chip agreement protocols 迈向片上网络协议协议

International Conference on Embedded Software Pub Date : 2012-10-07 DOI: 10.1145/2380356.2380395

Borislav Nikolic, Stefan M. Petters

引用次数: 12

Timed model checking with abstractions: towards worst-case response time analysis in resource-sharing manycore systems 基于抽象的时间模型检验:面向资源共享多核系统的最坏情况响应时间分析

International Conference on Embedded Software Pub Date : 2012-10-07 DOI: 10.1145/2380356.2380372

G. Giannopoulou, Kai Lampka, N. Stoimenov, L. Thiele

{"title":"Timed model checking with abstractions: towards worst-case response time analysis in resource-sharing manycore systems","authors":"G. Giannopoulou, Kai Lampka, N. Stoimenov, L. Thiele","doi":"10.1145/2380356.2380372","DOIUrl":"https://doi.org/10.1145/2380356.2380372","url":null,"abstract":"Multicore architectures are increasingly used nowadays in embedded real-time systems. Parallel execution of tasks feigns the possibility of a massive increase in performance. However, this is usually not achieved because of contention on shared resources. Concurrently executing tasks mutually block their accesses to the shared resource, causing non-deterministic delays. Timing analysis of tasks in such systems is then far from trivial. Recently, several analytic methods have been proposed for this purpose, however, they cannot model complex arbitration schemes such as FlexRay which is a common bus arbitration protocol in the automotive industry. This paper considers real-time tasks composed of superblocks, i.e., sequences of computation and resource accessing phases. Resource accesses such as accesses to memories and caches are synchronous, i.e., they cause execution on the processing core to stall until the access is served. For such systems, the paper presents a state-based modeling and analysis approach based on Timed Automata which can model accurately arbitration schemes of any complexity. Based on it, we compute safe bounds on the worst-case response times of tasks. The scalability of the approach is increased significantly by abstracting several cores and their tasks with one arrival curve, which represents their resource accesses and computation times. This curve is then incorporated into the Timed Automata model of the system. The accuracy and scalability of the approach are evaluated with a real-world application from the automotive industry and benchmark applications.","PeriodicalId":143573,"journal":{"name":"International Conference on Embedded Software","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117147039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49