评估NGMP多核处理器在空间领域的适用性

Mikel Fernández, R. Gioiosa, E. Quiñones, L. Fossati, Marco Zulianello, F. Cazorla
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引用次数: 67

摘要

多核处理器越来越被认为是提供未来安全关键型嵌入式系统所需性能的一种手段。在这方面,Aeroflex Gaisler与欧洲航天局(European Space Agency)合作开发了一种四核处理器NGMP,将用于该机构未来的太空任务。不幸的是,在工业领域中使用多核处理器并不简单,因为它对系统的定时行为提出了各种挑战。这主要是由于任务在访问硬件共享资源时受到干扰,这会影响它们的WCET。尽管多核共享资源中任务间干扰对实时应用的影响已经引起学术界的关注,但大多数解决方案都需要改变硬件。由于缺乏对实际COTS多核处理器上的任务间干扰对应用程序性能影响的定量研究,限制了其在工业上的应用。作为了解实际COTS处理器中任务间干扰影响的第一步,本文评估了NGMP的时间可预测性。特别是,我们测量了由于访问NGMP共享硬件资源的任务间干扰而导致的任务执行时间的最大变化。为此,我们使用一组专门的微基准测试来强调特定的处理器共享资源。研究结果可用于开发干扰感知的WCET估计方法和运行在嵌入式多核处理器上的实时应用程序的调度算法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Assessing the suitability of the NGMP multi-core processor in the space domain
Multi-core processors are increasingly being considered as a means to provide the performance required by future safety-critical embedded systems. In this line, Aeroflex Gaisler has developed, in conjunction with the European Space Agency, the NGMP, a quad-core processor to be used in the future space missions of the Agency. Unfortunately, the use of multi-core processors in industrial domains is not straightforward since it poses various challenges on the timing behavior of the system. This is mainly due to the interferences tasks suffer when accessing hardware shared resources and which can affect their WCET. Although the effect of inter-task interferences in multi-core shared resources on real-time applications has received attention from academia, most of the solutions proposed require hardware changes. The lack of quantitative studies of the slowdown on applications' performance caused by inter-task interferences on real COTS multi-core processors, limit their use by industry. As a first step to understand the effect of inter-task interference in real COTS processors, this paper evaluates the timing predictability properties of the NGMP. In particular, we measure the maximum variation on tasks' execution time due to inter-task interferences accessing NGMP's shared hardware resources. To that end, we use a set of specialized micro-benchmarks designed to stress specific processor shared resources. The results of this can be useful for developing interference-aware WCET estimation methodologies and scheduling algorithms for real-time applications running on embedded multi-core processors.
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