Proceedings of the 2016 International Symposium on Low Power Electronics and Design最新文献_第6页

Power--Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems 异构多核系统中并发应用的功率感知性能适应

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934612

Ali Aalsaud, R. Shafik, A. Rafiev, Fei Xia, Sheng Yang, A. Yakovlev

{"title":"Power--Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems","authors":"Ali Aalsaud, R. Shafik, A. Rafiev, Fei Xia, Sheng Yang, A. Yakovlev","doi":"10.1145/2934583.2934612","DOIUrl":"https://doi.org/10.1145/2934583.2934612","url":null,"abstract":"Modern embedded systems execute multiple applications, both sequentially and concurrently. These applications are exercised on heterogeneous platforms generating varying power consumption and system workloads (CPU or memory intensive or both). As a result, determining the most energy-efficient system configuration (i.e. the number of parallel threads, their core allocations and operating frequencies) tailored for each kind of workload and application scenario is extremely challenging. In this paper, we propose a novel runtime optimization approach with the aim of achieving maximized power normalized performance considering dynamic variation of workload and application scenarios. Fundamental to this approach is a comprehensive study to investigate the tradeoffs between inter-application concurrency with performance and power consumption under different system configurations. Using real experimental measurements on an Odroid XU-3 heterogeneous platform with a number of PARSEC benchmark applications, we model power normalized performance (in terms of IPS/Watt) underpinning analytical power and performance models, derived through multivariate linear regression (MLR). Using these models, we show that with increasing number of concurrent CPU intensive applications show variable gains in IPS/Watt compared to the memory intensive applications in both sequential and concurrent application scenarios. Furthermore, we demonstrate that it is possible to continuously adapt system configuration through a low-cost and linear-complexity runtime algorithm, which can improve the IPS/Watt by up to 125% compared to the existing approach.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128145709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches 通常关闭STT-MRAM缓存与零字节压缩节能的最后一级缓存

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934629

Fabian Oboril, F. Hameed, R. Bishnoi, A. Ahari, Helia Naeimi, M. Tahoori

引用次数: 6

Ferroelectric Transistor based Non-Volatile Flip-Flop 基于铁电晶体管的非易失性触发器

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934603

Danni Wang, Sumitha George, Ahmedullah Aziz, S. Datta, N. Vijaykrishnan, S. Gupta

{"title":"Ferroelectric Transistor based Non-Volatile Flip-Flop","authors":"Danni Wang, Sumitha George, Ahmedullah Aziz, S. Datta, N. Vijaykrishnan, S. Gupta","doi":"10.1145/2934583.2934603","DOIUrl":"https://doi.org/10.1145/2934583.2934603","url":null,"abstract":"We present a non-volatile flip-flop with a feature to back-up the state in a ferroelectric transistor (FEFET) during power failure or supply gating. The data is stored in the form of polarization of the ferroelectric (FE) layer in the gate stack of the FEFET. The proposed flip-flop utilizes the non-volatility of the three-terminal FEFET to optimize the data backup and restore operations. We perform an extensive device-circuit analysis to provide insights into the design of the proposed flip-flop. We discuss the optimization of the FE thickness in the gate stack of the FEFET to introduce suitable non-volatility and present the implications at the circuit level. Our analysis shows that by virtue of the three terminal structure of the FEFET and the order of magnitude difference in the current for the two polarization states, the design of the backup/restore module is considerably simplified. Compared to a FE capacitor based non-volatile flip-flop, the proposed flip-flop achieves 40%--50% smaller backup delay, 27%--40% lower backup energy, comparable restore delay and up to an order of magnitude lower restore energy. While the FE capacitor based design leads to 76% area penalty compared to a conventional (volatile) flip-flop, the proposed design incurs only 35% area overhead.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1932 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128017667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines 利用全集成电感式稳压器提高加密引擎侧信道电阻

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934607

Monodeep Kar, Arvind Singh, S. Mathew, Anand Rajan, V. De, S. Mukhopadhyay

引用次数: 21

DynSleep: Fine-grained Power Management for a Latency-Critical Data Center Application DynSleep:针对延迟关键型数据中心应用程序的细粒度电源管理

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934616

C. Chou, Daniel Wong, L. Bhuyan

{"title":"DynSleep: Fine-grained Power Management for a Latency-Critical Data Center Application","authors":"C. Chou, Daniel Wong, L. Bhuyan","doi":"10.1145/2934583.2934616","DOIUrl":"https://doi.org/10.1145/2934583.2934616","url":null,"abstract":"Servers running in datacenters are commonly kept underutilized to meet stringent latency targets. Due to poor energy-proportionality in commodity servers, the low utilization results in wasteful power consumption that cost millions of dollars. Applying dynamic power management on datacenter workloads is challenging, especially when tail latency requirements often fall in the sub-millisecond level. The fundamental issue is randomness due to unpredictable request arrival times and request service times. Prior techniques applied per-core DVFS to have fine-grain control of slowing down request processing without violating the tail latency target. However, most commodity servers only support per-core DFS, which greatly limits potential energy saving. In this paper, we propose DynSleep, a fine-grain power management scheme for datacenter workloads through the use of per-core sleep states (C-states). DynSleep dynamically postpones the processing of some requests, creating longer idle periods, which allow the use of deeper C-states to save energy. We design and implement DynSleep with Mem-cached, a popular key-value store application used in datacenters. The experimental results show that DynSleep achieves up to 65% core power saving, and 27% better than the per-core DVFS power management scheme, while still satisfying the tail latency constraint. To the best of our knowledge, this is the first work to analyze and develop power management technique with CPU C-states in latency-critical datacenter workloads","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131391357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Energy-Efficient Adaptive Classifier Design for Mobile Systems 移动系统节能自适应分类器设计

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934615

Zafar Takhirov, Joseph Wang, Venkatesh Saligrama, A. Joshi

引用次数: 13

Session details: Accelerators for Machine Learning

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/3256013

Rangharajan Venkatesan, Wei Wu

引用次数: 0

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs 解决门级单片3D ic中FEOL/BEOL退化的物理设计解决方案

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934622

B. W. Ku, P. Debacker, D. Milojevic, P. Raghavan, D. Verkest, A. Thean, S. Lim

{"title":"Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs","authors":"B. W. Ku, P. Debacker, D. Milojevic, P. Raghavan, D. Verkest, A. Thean, S. Lim","doi":"10.1145/2934583.2934622","DOIUrl":"https://doi.org/10.1145/2934583.2934622","url":null,"abstract":"In this paper, we develop physical design tools and methodologies to tackle the inter-tier performance variations caused by low temperature manufacturing in 2-tier gate-level monolithic 3D ICs (M3D). First, we model the top tier front-end-of-line (FEOL) device mobility degradation and its impact on cell delay/power values. Next, we quantify the impact of tungsten interconnect and cost-driven metal layer saving in the back-end-of-line (BEOL) of the bottom tier. These device and interconnect degradation models are used in our new full-chip M3D physical design flow named Derated 2D. This flow overcomes the well-known drawback of the state-of-the-art Shrunk 2D that requires shrinking of layout objects and RC parasitics. Also, Derated 2D performs low-temperature process-aware tier partitioning to effectively keep timing-critical components in the bottom tier. Moreover, Derated 2D conducts timing-driven monolithic inter-tier via (MIV) planning to cope with the resistivity increase in tungsten BEOL. Lastly, Derated 2D offers an effective timing closure solution through a post-route optimization. Experiments based on a foundry-grade 7nm FinFET process design kit (PDK) show that Derated 2D achieves up to 36% performance improvement and 10% energy saving compared with Shrunk 2D. Using a post-route optimization, Derated 2D further improves timing under various FEOL/BEOL degradation settings at a minimum energy overhead.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121187877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

An Efficient Parallel Scheduling Scheme on Multi-partition PCM Architecture 一种基于多分区PCM结构的高效并行调度方案

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934610

Wen Zhou, D. Feng, Yu Hua, Jingning Liu, Fangting Huang, Yu Chen

{"title":"An Efficient Parallel Scheduling Scheme on Multi-partition PCM Architecture","authors":"Wen Zhou, D. Feng, Yu Hua, Jingning Liu, Fangting Huang, Yu Chen","doi":"10.1145/2934583.2934610","DOIUrl":"https://doi.org/10.1145/2934583.2934610","url":null,"abstract":"Phase Change Memory (PCM) is an emerging non-volatile memory with the salient features of large-scale, high-speed, low-power and radiation resistance. It hence becomes an ideal candidate for the next-generation storage media of main memory. However, PCM suffers from inefficient I/O performance due to long write latency. Recent studies propose a multi-partition (or multi-subarray) architecture within each bank to enhance internal parallelism. However, conventional scheduling schemes fail to exploit the advantage of multiple partitions and incur inefficient bank utilization. In this paper, we propose a Write Priority overlap Read (WPoR) scheduling scheme which preferentially serves for a write request in one partition and allows other partitions to perform as many read requests as possible within this partition's program duration. Experimental results demonstrate that WPoR reduces the write latency by 24.7% (on average) compared with state-of-the-art scheduling algorithms. Meanwhile, the IPC indicator of WPoR scheduling increases respectively 6%, 7% and 26% (on average) compared with Read Priority, Write Pausing and Write Cancellation schemes.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Unified Power Frequency Model Framework 统一工频模型框架

Proceedings of the 2016 International Symposium on Low Power Electronics and Design Pub Date : 2016-08-08 DOI: 10.1145/2934583.2934605

Sriram Sundaram, Warren He, Sriram Sambamurthy, Aaron Grenat, Steven Liepe, S. Naffziger

{"title":"Unified Power Frequency Model Framework","authors":"Sriram Sundaram, Warren He, Sriram Sambamurthy, Aaron Grenat, Steven Liepe, S. Naffziger","doi":"10.1145/2934583.2934605","DOIUrl":"https://doi.org/10.1145/2934583.2934605","url":null,"abstract":"This paper describes a unified power-frequency model (UPFM) which combines analytical and empirical approaches to ensure a high degree of modeling flexibility and accuracy to measured silicon (Si) results. On one end, System-on-a-Chip (SoC) design teams focus the bulk of their efforts on using detailed low-level models to verify power consumption. Such models are available late in the design cycle, and often limited in number of workloads that can be evaluated. On the other end, FPGA-based modeling and spreadsheet approaches that operate on higher-level abstraction have been proposed. However these are often limited by poor correlation to measured Si results. In addition, extant models typically focus on power projection or prediction of Si speed but not both. A unified approach is much needed since SOCs today have to meet stringent power and performance constraints simultaneously. The proposed UPFM model overcomes these limitations. First actual measured Si results serve as the empirical baseline foundation for projections so that simulated vs. measured differences can be calibrated. Second, each IP is analytically modeled using a large number of relevant parameters. This high level of abstraction allows for the model to be useful from early design cycle all the way to the mature phase (parameters get refined over time). Also, wide-ranging parameters have been carefully chosen (and improved over multiple product generations) so that accuracy is not sacrificed. We demonstrate UPFM as a comprehensive framework where technology, architecture and infrastructure (test/thermal) choices can be modeled with high accuracy and drive optimal perf-per-watt SoC designs.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115756515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0