利用全集成电感式稳压器提高加密引擎侧信道电阻

Monodeep Kar, Arvind Singh, S. Mathew, Anand Rajan, V. De, S. Mukhopadhyay
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引用次数: 21

摘要

本文探讨了全集成电感电压调节器(FIVR)作为一种提高加密引擎侧信道电阻的技术。我们提出了低被动FIVR的安全感知设计模式,以提高加密引擎在时域和频域上对统计功率攻击的鲁棒性。利用相关功率分析方法对130纳米CMOS合成的128位AES引擎进行攻击。原始设计需要约250个测量来披露(MTD)密钥的第一个字节;但有了具有安全意识的FIVR,即使追踪了2万次,CPA也没有成功。我们提出了一种基于可逆性的威胁模型来改进基于FIVR的保护,并展示了安全感知FIVR对这种威胁的鲁棒性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines
This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of encryption engines. We propose security aware design modes for low passive FIVR to improve robustness of an encryption-engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used to attack a 128-bit AES engine synthesized in 130nm CMOS. The original design requires ~250 Measurements to Disclose (MTD) the 1st byte of key; but with security-aware FIVR, the CPA was unsuccessful even after 20,000 traces. We present a reversibility based threat model for the FIVR-based protection improvement and show the robustness of security aware FIVR against such threat.
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