Unified Power Frequency Model Framework

This paper describes a unified power-frequency model (UPFM) which combines analytical and empirical approaches to ensure a high degree of modeling flexibility and accuracy to measured silicon (Si) results. On one end, System-on-a-Chip (SoC) design teams focus the bulk of their efforts on using detailed low-level models to verify power consumption. Such models are available late in the design cycle, and often limited in number of workloads that can be evaluated. On the other end, FPGA-based modeling and spreadsheet approaches that operate on higher-level abstraction have been proposed. However these are often limited by poor correlation to measured Si results. In addition, extant models typically focus on power projection or prediction of Si speed but not both. A unified approach is much needed since SOCs today have to meet stringent power and performance constraints simultaneously. The proposed UPFM model overcomes these limitations. First actual measured Si results serve as the empirical baseline foundation for projections so that simulated vs. measured differences can be calibrated. Second, each IP is analytically modeled using a large number of relevant parameters. This high level of abstraction allows for the model to be useful from early design cycle all the way to the mature phase (parameters get refined over time). Also, wide-ranging parameters have been carefully chosen (and improved over multiple product generations) so that accuracy is not sacrificed. We demonstrate UPFM as a comprehensive framework where technology, architecture and infrastructure (test/thermal) choices can be modeled with high accuracy and drive optimal perf-per-watt SoC designs.