{"title":"In-situ polymer buildup monitoring in plasma etching systems [micromachined sensor]","authors":"J. Kim, K. D. Wise, J. Grizzle","doi":"10.1109/ISSM.1997.664506","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664506","url":null,"abstract":"This paper reports a micromachined sensor for the direct in-situ measurement of polymer buildup in plasma etching systems. The sensor is based on an electrothermal oscillator that measures the thermal mass change as polymer builds up on a stress-compensated dielectric window containing metal film heating and sensing resistors. The change in the thermal mass of the window can be detected as a variation in the pulse width (cooling time) of the oscillation. The device operates with a typical cooling time of 2.7 msec and has a measurement resolution of <1 nm. The device is flush-mounted in the chamber wall with the exposed window area protected by a thin film of iridium against damage by the plasma.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115876904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A cost-effective methodology for a run-by-run EWMA controller","authors":"R. Guo, Li-Shia Huang, Argon Chen, Jin-Jung Chen","doi":"10.1109/ISSM.1997.664624","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664624","url":null,"abstract":"In this paper, we present a cost-effective methodology for a run-by-run EWMA controller. This controller is an integrated approach that combines the advantages of statistical process control and feedback control. It adjusts the equipment settings only when the control chart detects an abnormal trend. Using simulations, we take into consideration the control sensitivity, robustness, and adjustment number required to determine an optimal weight for a minimum cost. As the simulation results demonstrate, the cost-effective run-by-run controller is able to keep drifting process outputs close to the target with only few runs of adjustment.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New technique of interlayer dielectric CMP with capping layer","authors":"K. Ishimoto, S. Tanaka, M. Kishimoto, Y. Itoh","doi":"10.1109/ISSM.1997.664601","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664601","url":null,"abstract":"A new technique of interlayer dielectric (ILD) planarization with chemical mechanical polishing (CMP) has been developed. The feature of this technique is to remove the step height more efficiently by making use of the polishing rate difference between two films deposited before CMP process. As compared to conventional process, the thickness of insulating layer before polishing can be reduced and the planarized surface can be obtained in shorter polishing time. This technique is one solution for CMP throughput and cost problem.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129304492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new CVD film formation process using ionization of TEOS","authors":"M. Adachi, T. Hayasi, T. Fujimoto, K. Okuyama","doi":"10.1109/ISSM.1997.664635","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664635","url":null,"abstract":"A new CVD method called ionization CVD, where ionized source molecules were deposited on a substrate by Coulombic force, was developed to control film formation and particle generation. This method was applied to the TEOS/O/sub 3/-APCVD process by using the surface corona discharge. The growth rate of film formed by the ionization CVD was 2-4 times higher than that by the common CVD. Films deposited by the new CVD showed strongly the flow-like shape. Nanometer-sized particles which have been generally generated in the common reactor, were not detected in the ionization CVD reactor.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"72 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128025297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The impact of lot-to-lot and wafer-to-wafer variations on SPC","authors":"R. Nurani, J. Shanthikumar","doi":"10.1109/ISSM.1997.664627","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664627","url":null,"abstract":"In this paper we point out that the application of standard SPC charts for process control during wafer fabrication could lead to errors due to the presence of the lot-to-lot and wafer-to-wafer variations. We illustrate that the error could increase the \"lots-at-risk\" by as much as 17%. We present a new SPC model which accounts for the lot-to-lot and wafer-to-wafer variations. Then, we present an adaptive sequential two-lot control policy, where we sample the successive lot when there is an out-of-control signal, and investigate for the process shift only when the successive lot also gives an out-of-control signal. This adaptive method outperforms the static policy as long as the lot-to-lot variance is smaller than the wafer-to-wafer variance. However, when the wafer-to-wafer variance is higher than the lot-to-lot variance, the information from a successive lot is less variance than the information from additional wafers in the same lot.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133619950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A better choice-a fuzzy logic based lot sequencing decision support system for operators in a job shop fab with reentrant process flows","authors":"F. Roobeek","doi":"10.1109/ISSM.1997.664489","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664489","url":null,"abstract":"Significant reduction of cycle times can be achieved by removing barriers. Cross training, cross functional teams, leveled production, starts control, bottle-neck management and so on are the well known ways that help to improve the process. No matter how well this matter is dealt with, disturbances will occur in any waferfab. The only way operators can still influence the fabs cycle time performance is by making the right choices when selecting which equipment to operate first and which lot(s) to process next. This is a difficult task, since many factors should be taken into account, particularly in mixed volume, mixed process, mixed product fabs with reentrant process flows. As part of the research program ABC, A Better Choice, a fuzzy logic based lot sequencing decision support system has been developed and implemented. Heuristics as well as theory were used in its design. The DSS has brought significant benefits in a fully loaded fab in terms of more outs, while retaining a good cycle time.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"184 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133355608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Spatially resolved endpoint detector for plasma etcher","authors":"R. Chen, S. Rangan, C. Spanos","doi":"10.1109/ISSM.1997.664508","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664508","url":null,"abstract":"In this paper we present a novel spatially resolved sensor to detect the endpoint and monitor spatial uniformity for a plasma etching process. A scanning spatially-resolved optical emission spectroscopy (SROES) system was built and installed in Berkeley's Microfabrication Laboratory. This sensor system consists of a stepper motor, controller, and a monochrometer, which provides an in-situ real-time monitoring of the etching endpoint spatially. In this paper, we show the promise of this spatially-resolved endpoint detector, and explain our hardware design and the future experiment plan.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122911470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
John Musacchio, Sundeep Rangan, C. Spanos, K. Poolla
{"title":"On the utility of run to run control in semiconductor manufacturing","authors":"John Musacchio, Sundeep Rangan, C. Spanos, K. Poolla","doi":"10.1109/ISSM.1997.664523","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664523","url":null,"abstract":"Run to Run (RTR) control uses data from past process runs to adjust settings for the next run. By making better use of existing in-line metrology and actuation capabilities, RTR control offers the potential of reducing variability in manufacturing with minimal capital cost. In this paper, we survey the types of equipment models that can be used for RTR control, compare existing RTR control algorithms, and discuss issues affecting the potential utility of RTR control.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. H. Bennett, J. Garvin, J. Hightower, D. Coldren, M. Reddy
{"title":"In-line automatic defect classification [wafer fabrication]","authors":"M. H. Bennett, J. Garvin, J. Hightower, D. Coldren, M. Reddy","doi":"10.1109/ISSM.1997.664582","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664582","url":null,"abstract":"Manual review of wafers and classification of defects is a slow, tedious process. While identification of defects is important, this step in wafer fabrication can be a bottleneck to throughput. The accuracy of human classification can vary from day to day, and person to person. In-Line Automatic Defect Classification (ADC) is an emerging technology aimed at solving this problem.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128493180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving cycle time through managing variability in a DRAM production line","authors":"A. Majorana, G. Iuliano","doi":"10.1109/ISSM.1997.664487","DOIUrl":"https://doi.org/10.1109/ISSM.1997.664487","url":null,"abstract":"The authors describe the process adopted to improve productivity in terms of cycle time decrease in a DRAM wafer fab (AMOS, Texas Instruments Italy). In order to arrange the structural and managerial factors influencing the cycle time of products, an integrated approach aimed to contain the variability is outlined. Such a process generated a 30% cycle time reduction in 1996 with a remarkable impact on the operating performance of the factory.","PeriodicalId":138267,"journal":{"name":"1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124335825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}