2008 International Conference on Field Programmable Logic and Applications最新文献_第6页

Automatic generation of run-time parameterizable configurations 自动生成运行时可参数化配置

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629964

Karel Bruneel, D. Stroobandt

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引用次数: 33

Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform 异构可重构平台上并行执行的资源分配算法和OpenMP扩展

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630031

V. Sima, E. Panainte, K. Bertels

引用次数: 5

SPP1148 booth: Network processors SPP1148展位:网络处理器

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629960

Thilo Pionteck, R. Koch, C. Albrecht, E. Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, A. Herkersdorf

引用次数: 3

An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC 基于fpga的混合多处理器SOC架构综合与应用映射的ILP公式

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629981

Jason Wu, John W. Williams, N. Bergmann

引用次数: 4

Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor 嵌入式fpga指令集处理器内存地址变换器的应用自适应重构

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1142/S0218126610006748

Youngsu Kwon, N. Eum

{"title":"Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor","authors":"Youngsu Kwon, N. Eum","doi":"10.1142/S0218126610006748","DOIUrl":"https://doi.org/10.1142/S0218126610006748","url":null,"abstract":"Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, the memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler to be integrated in the memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm reallocates the decomposed memory sub-pages based on the access conflict graph obtained by profiling the memory access pattern of the application to produce the synthesizable code. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler reduces the amount of access conflicts by 80% on average utilizing 1592 LUTs which is 14% of that of the processor.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128083540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A technique for minimizing power during FPGA placement 在FPGA放置过程中最小化功耗的技术

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629937

Kristofer Vorwerk, Madhu Raman, J. Dunoyer, Yaun-Chung Hsu, A. Kundu, A. Kennings

引用次数: 19

Cluster architecture based on low cost reconfigurable hardware 基于低成本可重构硬件的集群架构

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630017

C. Pedraza, Emilio Castillo, J. Castillo, C. Camarero, J. L. Bosque, J. Martínez, R. M. D. Llano

引用次数: 14

ATCA-based computation platform for data acquisition and triggering in particle physics experiments 基于atca的粒子物理实验数据采集与触发计算平台

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629946

Ming Liu, J. Lang, Shuo Yang, T. Perez, W. Kuehn, Hao Xu, D. Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, A. Jantsch

引用次数: 17

GICS: Generic interconnection system GICS:通用互连系统

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629942

Tamas Malek, Tomáš Martínek, J. Korenek

引用次数: 6

Numerical function generators using bilinear interpolation 使用双线性插值的数值函数生成器

2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629984

Shinobu Nagayama, Tsutomu Sasao, J. T. Butler

引用次数: 3