GICS: Generic interconnection system

Abstract

The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application. The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 technology.